Lab 8 - ECE 421L 

Authored by:

Michael Kajkowski kajkowsk@unlv.nevada.edu

Jason Sikorski sikorsk4@unlv.nevada.edu

Eduardo Hoyuela-Alcaraz hoyuelaa@unlv.nevada.edu

11/29/2014

 

 

 For this lab we will generate a test chip layout for submission to MOSIS for fabrication.

 

 Here are the devices that we will include on our test chip:

 

    

 

Ground will be pin20

   

 30u/.6u NMOS:

nmos_layout.JPG

   

Connections:

SN-pin27 (connect ground)

DN-pin28 (measure drain current using this pin)

GN-pin29 (connect small voltage to gate)

BN-pin20 (connect ground)

  

30u/.6u PMOS:

pmos_layout.JPG

     

Connections:

GP-pin26 (connect small gate voltage)

BP-pin25 (connect 5 volts)

SP-pin24 (connect 5 volts)

DP-pin23 (measure drain current using this pin)

   

Inverter 60u/30u:

inverter_60_30_layout.JPG

 

Connections:

VDD-pin16 (connect 5 volts)

GND-pin20 (connect ground)

A-pin17 (input a square wave using function generator)

Ai-pin15 (measure output using oscillscope)

 You will want to compare, using oscillscope, pin 17 and pin 15

Inverter 6u/6u:

inverter_6_6_layout.JPG

 

Connections:

VDD-pin13 (connect 5 volts)

GND-pin20 (connect ground)

A-pin14 (input a square wave using function generator)

Ai-pin12 (measure output using oscillscope)

  You will want to compare, using oscillscope, pin 14 and pin 12  

 
 
 

 

You will need to use an ohm meter to measure all resistors. The negative terminal of ohm meter will always connect to pin 20.

20k hi-res poly resistor:

20k_hi_res_poly_layout.JPG

 

Connections:

R-pin11 (connect 5 volts)

L-pin20 (connect ground)

 

20k n-well resistor:

20k_nwell_layout.JPG

 

Connections:

R-pin10 (connect 5 volts)

L-pin20 (connect ground)

 

1k n+ resistor: 

1k_n_plus.JPG

 

Connections:

R-pin9 (connect 5 volts)

L-pin20 (connect ground)

 

   

1k p+ resistor:

1k_p_plus.JPG

   

   

Connections:

R-pin7 (connect 5 volts)

L-pin20 (connect ground)

VDD-pin8 (connect 5 volts)

 

   

Ring Oscillator:

ring_osc_layout.JPG

     

Connections:

VDD-pin18 (connect 5 volts)

GND-pin20 (connect to ground)

OSC_out-pin19 (connect this pin to oscillscope and observe output)

     

   

Band Gap:

bandgap_layout.JPG

   

Connections:

VDD-pin22 (connect 5 volts)

GND-pin20 (connect to ground)

Vref-pin21 (using ohm meter, negative terminal to pin 20 & plus terminal to pin 21, we should see 5 volts)

 

     

Here are the pad assignments that we used:

pin_assignments.JPG

     

Here is the completed chip layout:

 chip_layout.JPG

 

 Chip Schematic:

 chip_schematic.JPG

   

   

   

THIS CONCLUDES LAB 8. 

       

        

        

Here is the lab 8 project directory: MOSIS_chip3.zip

              

MAKE SURE TO BACK UP ALL OF YOUR LAB 8 CONTENTS 

(zip and email your work to yourself).

        

backup.PNG

 

 

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