Lab 8 - ECE 421L 

Authored by:

Michael Kajkowski kajkowsk@unlv.nevada.edu

Jason Sikorski sikorsk4@unlv.nevada.edu

Eduardo Hoyuela-Alcaraz hoyuelaa@unlv.nevada.edu

11/29/2014

 For this lab we will generate a test chip layout for submission to MOSIS for fabrication.

 Here are the devices that we will include on our test chip:

• 30u/0.6u NMOS (3 pins, DN, GN, SN, connect the p+ body, B, of the NMOS to the chip's ground pin)
• 30u/0.6u PMOS (4 pins, DP, GP, SP, and BP)
• Inverter made using 30u/60u NMOS and 6u/6u PMOS (3 pins, in, out, VDD_inv)
• 61 stage ring oscillator using 6u/0.6u MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
• 20k n-well resistor (2 pins)
• 20k hi-res poly resistor (2 pins) 
• 1k n+ resistor (2 pins)
• 1k p+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)
• Bandgap reference (2 pins, VDD_bg and Vref)

Ground will be pin20

 30u/.6u NMOS:

Connections:

SN-pin27 (connect ground)

DN-pin28 (measure drain current using this pin)

GN-pin29 (connect small voltage to gate)

BN-pin20 (connect ground)

30u/.6u PMOS:

Connections:

GP-pin26 (connect small gate voltage)

BP-pin25 (connect 5 volts)

SP-pin24 (connect 5 volts)

DP-pin23 (measure drain current using this pin)

Inverter 60u/30u:

Connections:

VDD-pin16 (connect 5 volts)

GND-pin20 (connect ground)

A-pin17 (input a square wave using function generator)

Ai-pin15 (measure output using oscillscope)

 You will want to compare, using oscillscope, pin 17 and pin 15

Inverter 6u/6u:

Connections:

VDD-pin13 (connect 5 volts)

GND-pin20 (connect ground)

A-pin14 (input a square wave using function generator)

Ai-pin12 (measure output using oscillscope)

  You will want to compare, using oscillscope, pin 14 and pin 12  

You will need to use an ohm meter to measure all resistors. The negative terminal of ohm meter will always connect to pin 20.

20k hi-res poly resistor:

Connections:

R-pin11 (connect 5 volts)

L-pin20 (connect ground)

20k n-well resistor:

Connections:

R-pin10 (connect 5 volts)

L-pin20 (connect ground)

1k n+ resistor: 

Connections:

R-pin9 (connect 5 volts)

L-pin20 (connect ground)

1k p+ resistor:

Connections:

R-pin7 (connect 5 volts)

L-pin20 (connect ground)

VDD-pin8 (connect 5 volts)

Ring Oscillator:

Connections:

VDD-pin18 (connect 5 volts)

GND-pin20 (connect to ground)

OSC_out-pin19 (connect this pin to oscillscope and observe output)

Band Gap:

Connections:

VDD-pin22 (connect 5 volts)

GND-pin20 (connect to ground)

Vref-pin21 (using ohm meter, negative terminal to pin 20 & plus terminal to pin 21, we should see 5 volts)

Here are the pad assignments that we used:

Here is the completed chip layout:

 Chip Schematic:

THIS CONCLUDES LAB 8. 

Here is the lab 8 project directory: MOSIS_chip3.zip

MAKE SURE TO BACK UP ALL OF YOUR LAB 8 CONTENTS 

(zip and email your work to yourself).

Return to EE421L Labs