Lab 1 - Laboratory introduction, generating/posting html lab reports
Lab 3 - Layout of a 10-bit digital-to-analog converter (DAC)
Lab 4 - IV Characteristics and layout of NMOS and PMOS devices in ON's C5 Process
Lab 5 - Design, layout, and simulation of a CMOS inverter
Lab 6 - Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full Adder
Lab 7 - Using buses and arrays in the design of word Inverters, Muxes, and High-speed Adders
Lab 8 - Generating a test chip layout for submission to MOSIS for fabrication
Final Project - Design, layout, and simulation of an 8-bit ALU that can perform: A AND B, A OR B, A + B (addition), A - B (subtraction).
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