The schematic for the NAND gate is exactly the same so we can just open it and do a check and save to make sure everything passes.
The symbol is also the same except I need to add the label identifying it as mine.
The next thing we need to do is modify the layout for the NAND gate we created in the tutorial so it serves our purpose for this lab. Since we are going to be using it in many different layouts we should space out the vdd and gnd busses so that they will be a uniform distance for all the following layouts we do. This will allow us to easily connect different layouts to one another as we will see later.
Next we extract.
Then we can do a quick DRC and LVS check to make sure everything matches up.
Next thing is to build the schematic for the XOR gate so that it matches the schematic in figure 12.18 in the book.
From there we create a symbol.
Next is the layout. The busses will be placed the same distance apart as the NAND gate so we can connect them together later in the adder.
Then we extract.
Now we can do a quick DRC and LVS to make sure everything matches.
Now that we have the NAND and XOR gates, we need to test them so make a new cell called sim_gates and open the schematic. We are also going to test the inverter we made in a previous lab. To test all the different combinations possible we will put in two vpulse sources. One will be set to 20ns pulses with 40ns periods and the other will be set to 40ns pulses with 80ns periods. We have to make sure that rising and falling edges are very precise or it may cause the gates to act in a manner we don't want. If one pulse rises and falls slightly faster or slower than the other one, the gates will give false outputs. to fix this the rise and fall time have been set to 1ps.
Once we check and save we can set up the ADE. Once open we can load the NMOS and PMOS models and set the analysis to a 200ns transient. Select the outputs to be plotted and we are good to go.
Press the green arrow and this is the plot that appears. You can see that every different combination of A and B are present and the gates we made are working exactly as designed.
Full Adder
Now tha we have working NAND and XOR gates we can implement them in a full adder. The first thing we can do is make a schematic that matches the one supplied in the lab directions.
We now need to make a symbol similiar to the one in the lab directions.
Now comes the hard part. We need to make the layout for the full adder. In making our NAND and XOR layouts we tried to make it as easy as possible to connect them up but there will still be some difficulties routing all the signals. All we do now is design the layout to match the schematic.
Extract.
Now we do a quick DRC and LVS to make sure everything matches.
Everything matches so now we can move on to testing it. After creating a new cell called sim_full_adder we can make up a test circuit. It is similiar to the test circuit we made for testing the gates so we can copy over the vdd and pulse sources. The pulse sources will connect to A and B while we make another pulse source with half the period of B to connect to cin.
After a check and save we can set up the ADE. We can copy over the spectre state from the gate sim and that will make things a little easier. Change the sim time to 100ns and select a, b, cin, cout, and s to be plotted.
Press the green arrow and this is the plot that appears. You can see that every different combination of a, b, and cin are present and the gates we made are working exactly as designed.
Here is the truth table for the adder for comparison.
This concludes Lab 6. As always, I zip up my lab directory and webpage files then backup my files on Google Drive.
Here is a copy of the directory I used in this lab.
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