The next step is to create a schematic labeled NMOS_IV_3 and open it. The title indicates that the transistor is going to have 3 terminals. Once it opens, we are going to place a NMOS transistor from the NCSU database with a width of 6u and a length of 600nm.
Then we are going to add input/output pins labeled S, D, and G. Once we do that we can check and save. If everything passes we need to create a symbol for this transistor so will select Create-->Cell View-->From Cell View to make a symbol for the 3-terminal transistor.
We next need to draw the symbol so it matches the basic structure of the NMOS transistor with the pins in the correct place.
Once the symbol is complete, close everything and create a new schematic labeled sim_NMOS_IV_3.
Add in the NMOS cell just created and put in a couple voltage sources as shown in the tutorial.
Next we need to open ADE and select the model for the NMOS. We are going to go into the library setup and select the nmos model inside the ami06 library.
Once that is selected we need to define the VGS variable. Select Variables-->Edit and then enter in VGS and a value of zero. then press Add.
Next we need to add a DC sweep. We are going to do a linear sweep along the V1 component parameter from 0 to 5 with 1m increments. We also need to select the D output of the transistor as our output point.
Next we need to setup the parametric analysis. We are going to sweep the VGS variable from 0 to 5 with steps of 1. Once we have that set up, hit the run button and we get the following plot of the IV curves for the NMOS. This is the ID vs VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 in 1 mV steps.
Now that we have an understanding of what the IV characteristics are, we need to make a layout for the NMOS. Create a layout under the NMOS_IV_3 cellview. Once opened, press I and go to NCSU_TechLib_ami06 and select the nmos. Before it is placed make sure the width is set to 6um and the length set to 600nm. Once that is done place it on to the layout.
Next, we need to add a PTAP to ground the substrate. Press I and add the ptap to the layout. Next add the m1_poly to the layout, connect the poly to the poly of the NMOS, and then DRC.
We need to add pins to connect the NMOS to the outside world. Connect the left side to the PTAP and label it S. Make a pin coming out of the right side labeled D. Make a pin labeled G that covers the metal_1 portion of the m1_poly. DRC to check for errors.
If it passes DRC we can extract the layout. Select Verify-->Extract. Close the layout and open the extracted view to see what we get.
If we LVS we will see that it fails because the Bulk needs to be tied to ground. We need to go back in to the layout and fix this problem.
Instead of the left side connecting to the PTAP we need to make it just like the right side and keep the S label. We will then make a new pin labeled gnd! and put it over the metal_1 layer of the PTAP. This will connect our bulk to ground and it should then pass the LVS.
It still won't pass the LVS however because it is looking for a 4-terminal transistor. If we go back to the schematic of the NMOS we can change the cell name to nmos4. this will give us a 4th connection that we can connect to gnd! and re run the LVS. With this final change the LVS will match and we can continue on.
Now that the netlists match we can run the IV characteristics again. The setup is exactly the same as before except we need to change the environment options to simulate from the extracted view instead of the schematic.
Following similiar steps we are going to create a 4-terminal PMOS with a width of 12um and a length of 600nm. First thing is to create a schematic for the PMOS.
From that we can create a symbol with all the matching pins.
Next we are going to create a layout. Instantiate the pmos symbol from the NCSU ami06 library with a width of 12um and a length of 600nm. Add the necessary pins and DRC.
Next we are going to create a sim circuit similiar to the one in Tutorial 2.
Once that sim circuit is created open ADE and we are going to test it just like we did the NMOS. We need to set the model to the ami06 PMOS model, Add the VSG variable with a value of 0, and do a dc analysis with linear steps on V2 from 0 to 5 with 1m steps. Finally, we need to select the S terminal of the transistor to be the plotted output.
Next we are going to do a parametric analysis with the value of VSG sweeping from 0 to 5 with steps of 1. Hit run and we get the following plot of the IV characteristics. This is the ID vs VSD of a PMOS device for VSG varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 in 1 mV steps.
This concludes Tutorial 2 . It gives us an idea of how to build and test NMOS and PMOS transistors.
In the next part of the lab, we are going to modify the 4-terminal NMOS and PMOS transistor simulations we have already made.
Copy over everything from Tutorial 2 into a new library labeled lab4. Change the name of NMOS_IV to 6u_600n_NMOS_IV and change PMOS_IV to 12u_600n_PMOS_IV. Open sim_NMOS_IV and change the value of the right voltage source to VDS.
Check and save then open ADE and load the previous saved state. Once it loads, add the variable VDS and make it equal to 100m. Change the dc sweep to go from 0 to 2 with 1m steps.
Conduct the DC sweep and you will get the following plot. Since VDS is constant we don't need to do a parametric sweep like before. This is the ID vs VGS of an NMOS device for VDS = 100mV where VGS varies from 0 to 2 V in 1mV steps.
Close everything and open sim_PMOS_IV. Change the voltage source in the middle to equal VSD. Check and Save.
Open ADE and load the previous saved state. Add the variable VSD and set it to 100m. Next, change the dc sweep to go from 0 to 2 with 1m steps.
Once that is all set, run the DC sweep and this is the plot we get. This is the ID vs VSG of a PMOS device for VDS = 100mV where VGS varies from 0 to 2 V in 1mV steps.
In the next part of this lab we will be adding probe pads to the NMOS and PMOS layouts. This will allow us to probe the pins of the transistors and see what is going on.
First we are going to copy over the probe pad cell from .zip file provided in the Lab 4 directions to the lab4 directory we have been working in.
Open up the schematic for 6u_600n_NMOS_IV. We are going to add 4 probe pads to the schematic each connected to one of the pins.
Check and save then open the layout. We need to add 4 pads to the layout to match the schematic. Since the transistor is using metal_1 and the probe pads are using metal_3 we need to create a few transitions to go from metal_1 to metal_2 and then from metal_2 to metal_3. This is a close up of the transistor with those transitions.
Here is the entire layout.
After a DRC and LVS we can see that everything is correct.
Now we need to do the same thing with the PMOS schematic and layout. First open the schematic and add the 4 probe pads just like the NMOS.
Add the 4 probe pads to the layout with the connections and transitions just like the NMOS. Here is a close-up of the transistor and connections.
Here is the entire layout.
Finally we need to DRC and LVS to make sure everything is correct.
This concludes Lab 4. We now have a 4-terminal PMOS and a 4-terminal NMOS transistor complete with IV characteristics, schematics, and layouts including probe pads for testing purposes.
Once everything is completed we need to zip up and save both the cadence directory and the webpage directory.
Here is the directory for Lab 4
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