Lab 2   EE 421L

Prelab:

First thing to do is download lab2.zip to the desktop from the lab page and unzip it into the CMOSedu folder created previously. Once that is done, start Virtuoso, open the library manager, and go to sim_Ideal_ADC_DAC --> schematic.
 

 
Launch ADE and load the previous saved state. Run the simulation and you should get something like this:
 

 
It takes the smooth input and gives a discrete output in the same general shape. That concludes the prelab.

Lab 2:

The first thing to do is create a new cell called R_2R and create a schematic. In this schematic we will have the input connected to two 10k resistors connected in series that will then hit a junction. Going out the top will just be a pin connection and going out the bottom the signal will go through another 10k resistor.
 


 
Next we have to make a symbol for the new R_2R. Following the names we gave the pins on the schematic we will make a symbol with pins for "in", "top", and "bottom"
 
 

 
Next we are going to make a copy of the Ideal_10-bit_DAC and rename it MY_10-bit_DAC. This will copy over all the pin connections we are going to need for making a resistive DAC. After deleting everything except the pins B0-B9 and Vout, we can insert the symbol we just made into the schematic. Following the layout given in figure 30.14 we connect the symbols in series with each input pin connected to one of the "B" pins. The top output of the final R_2R will connect to the Vout pin.
 
 

 
If you look at the design given in figure 30.14 you can see that if you start at the bottom, because the pins B0-B8 are grounded as well, you will end up with a large series/parallel resistor network that will reduce down to the value of "R" or 10k.
 
The next thing to do is change the symbol for MY_10-bit_DAC because there are several pins that are no longer used.
 

 
Now that we have made all the changed we can test the delay. After making a copy of sim_Ideal_ADC_DAC, renaming it sim_Ideal_ADC_MY_DAC, and linking the new DAC we need to change the schematic. We first delete everything that isn't the DAC, short pins B0-B8 to ground, and connect B9 to a pulse input we run a transient test and find how long it takes to get to the value for the delay time.
 
 
From that we can see that at 74.358ns we will reach Vout/2. If we compare that to the formula we use to calculate delay time (Td=0.7RC) we find that it will also give us around 70ns. In this simulation we are using the 10k resistor value from the DAC and a 10pF capacitor for the load.
 
0.7 x 10^4 x 10^-11 = 70ns
 
The next thing to do is go back to the original design for the ADC_DAC sim and make sure we get the same output with the new DAC as we did with the old DAC. This is the output of the same sim with the new DAC instead of the old one.


 
Now that we know it works the same as the old one we can test different loads and see what effect they have on the circuit. First we will test a 10k resistive load.
 

 
If you look at the output for this circuit it will look like original output except the amplitude will be smaller because of the 10k resistive load.
 

 
Next we are going to try a 10pF capacitive load.
 

 
This load will do three things. First, it will smooth the output because of the capacitor charging and discharging. Second, because of this smoothing, it will delay the signal. Thirdly, because of the impedance of the capacitor, it will also decrease the amplitude of the output signal.
 

 
Lastly, we will have the 10k resistive load as well as the 10pF capacitive load both connected.
 

 
Based on what we know about both of these independently, we can assume that the output will be decreased significantly, smoother, and will also have a delay.
 

 
If the resistance of the switches in figure 30.14 are not small compared to R it will make the resistance of the DAC higher and will make both the delay time longer and the output will have a smaller amplitude.

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