Lab 8 - EE 421L
Cesar Macias
Stephen Berta
Braxon Tawatao
maciasc4@unlv.nevada.edu
12-1-2014
Chip design
For
this project our global ground will be pin (20) the number between the
parentheses denotes the pin number for the part being described
![](pinlanyout.jpg)
Pmos: drain(7), body (6), source(5), gate(4)
![](pmos.PNG)
Resitor 20k polu (37-38)
![](r20kpoly.PNG)
R 20k nwell (36-37)
![](r20knwell.PNG)
andgap: VDD-bg(19), vref(18)
![](bandgap.PNG)
inverter: vdd_inv(21), in(22), out(23)
![](inverter.PNG)
NMOS: drain(15), gate(16), source(17)
![](nmos.PNG)
Resistor 1k n+ (38-39)
![](r1knplus.PNG)
Resistor 1K p+(39-40)
![](r1kpplus.PNG)
Charge pump: out(24), vdd(25)
![](chargepump.PNG)
ALU: cin(14), in1(13), in2(12), s<0>(11), s<1>(10), cout(9), out(8), vdd_alu(3)
![](ALU.PNG)
61 stage ring oscillator: VDD_osc(28) osc-out(29)
![](61ringosc.PNG)
Full chip project
![](FULLCHIP.PNG)
The files for this lab can be found here.
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