Lab 7 - EE 421L 

Cesar Macias

maciasc4@unlv.nevada.edu      

10-26-2014

Using buses and arrays in the design of word inverters, muxes, and high-speed adders

We first create a 4 bit inverter to demonstrate the use of buses. The shematic can be seen below

This can be more consice by the use of buses and making the specifying the size of the instance when instering the piece (IO<from:to>) the same schematic as the previous can be seen using buses.

symbol of previosu schematic

we will now simulate this piece and put different size capacitor in each of the ouputs

From the simulations results we can see the teh bigger the capacitor the longer it takes for the signal to change (charge and discharge) and we can grab a specific signal from the bus without having to do multiple simulations.

We will now create multiple logic gates that use 8 bit size inputs and outputs

NAND:

schematic

this is the symbol for the 2 bit NAND symbol

and the schematic for the NAND 8 bit gate

NOR:

schematic

2 bit symbol

and the 8 bit schematic

OR:

schematic

2 bit symbol

and the or 8 bit schematic

AND:

schematic

2 bit symbol

and the 8 bit schematic

INVERTER:

schematic

single input single output symbol

and the 8 bit schematic

We can now run a simulation of the gates, it's possible to run it in a single schematic as we did below.

Simulation results can be seen below

Now we will work on the MUX
   
The operation of the MUX is really simple, if high is selected then A is the output and if Low is selected the B is the output. The demultiplexer works the same but opposite. When S is high, then the output will be A but when S is low then the output will be B.


Now the 8 bit wordsize mux  and demux will work the same except this time the lengt of the input and outputs is eight bits long.
8bit multiplexer schematic


We selected just a couple of output to demostrate that the multiplexer works, it is not necessary to have 8 bit word sizes since for demostration purposes all the bits contain the same information. The same will be done to the demux for simplicity purposes.


We will now do an 8 bit full adder, we will star by making a 2 bit adder that includes a carry in and a carry out, the schematic can be seen below

This is the layour for the full adder


Now using this full adder we will creaste an 8 bit adder by cascading the carry outs, the schematic for the 8 bit can be seen below.


by using buses we connect the carry out from 0 to 6 the the carry in and carry in 0 is separate.
this is the symbol for the 8 bit full adder

this is the test schematic

this are the simulated  results, I tried using the most general  test  possible  that  will  test all  possible  cases.   I used 1111,1111 + 0000,0000 and a carry in of 1 after a set time. At first we can see the the output is 1111,1111 carry out 0 but once the carry in is included we get 0000,0000 carry out 1 so it added all the numbers are succesfully and carried out the 1.  Feel  free  to  test  the  adder as  necessary.

The layout and proof of LVS can be seen below.




Now we will back up this lab


The files for this lab can be found here.

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