Lab 6 - EE 421L 

Cesar Macias

maciasc4@unlv.nevada.edu      

10-19-2014

In this lab we will create a full adder using nmos and Pmos

We first start with a simple inverter

This is the schematic for the inverter. For this whole lab we will be using 6u/600n NMOS and PMOS

We then LVS

Now we create a NAND gate, the schematic can be seen below

Symbol for nand gate

Layout for this nand Gate

This is the symbol for the XOR

We then LVS it

We are now going to simulate all the gates we created to make sure they work. the schematic used to simulate them can be seen below. We use pulse A and pulse, B whos frequency is twice as fast as A to simulate inputs 00,01,10,11

The output can be seen below, all out gates are working as expected.

It is important to realize there is a rise time and a fall time in this switching between signals. If we look at around the 200 ns mark we can see a glitch, that is because the numbers are in transition from 01 to 10 but what in between that time the computer is only reading 00, so  0 or 0 is zero as seen in this glitch.

Out layout is seen below, we routed VDD and GND and we have 1 NAND, followed by 2 XOR's which are then again followed by two NAND's

To simulate it we use the same technique as before when A is has a base frequency and B is twice as fast as A. Cin is also twice as fast a B.

We can now see that the output is as expected.

0+0=0

0+1=1

1+1=0, carry out 1 etc...

backup

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