Lab 5 - EE 421L 

Cesar Macias

maciasc4@unlv.nevada.edu      

10-9-2014

In this lab we will design an inverter using CMOS and check how capacitace affects such inverter.

First we layed out the schmatic for a 12u/6u (PMOS/NMOS width) by 600nm inverter.

A will be the regular input and Ai is in inverted input.

We then proced to make the layout for this inverter.

 We extract it and LVS it until net-list match. Picture is shown below.

We then do the same for a different size inverter. This time the PMOS/NMOS size is 48u/24u.

To make the PMOS/NMOS such size, we just use the mutiplier (m) and multply it by 4.

Check and save and create a symbol (seen below)

This is the layout for the inverter

we then extract it and LVS as we did it for the smaller inverter.

We will now simulate both inverters and compare. We are going to use regular Spectre and then we will use Ultrasim which is a fast mode simulaion for cadence. We expect the Spectre to be more accurate and detailed, and the Ultrasim to be accurate but more "choppy"

 We will be using this circuit to run the simulations (see below)

100f

1p

10p

100p

First we can see that the smaller the capacitance load, the faster the charge and discharge. We can also see that the 48u/24u inverter seems to charge and discharge faster and that is because the increase width allows more current to pass through and chargind and discharging becomes faster.

 Now we will repeat the simulations using Ultrasim

capacitance	inverter 1	inverter 2
100f
1p
10p
100p

So Ultrasim is a little less accurate but if it's a big circuit you can get good results even if they are not perfect.

Now we will back up this lab to dropbox

click here to download lab 5

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