Lab 4 - EE 421L
Cesar Macias
maciasc4@unlv.nevada.edu
10-3-2014
The outcome of this lab is to create schematic and layouts for PMOS and NMOS and simulate the current (ID) vs the drain to source voltage (VDS) and gate to source voltage (VGS).
Schematic for PMOS simulation
note the NMOS has a W/L ratio of 6u/600n.
ID vs VDS for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps
This simulation had to be done the parametric analysis tool.
ID vs VGS of an NMOS when VDS=100 mV.
Schematic for PMOS
ID vs VSD f a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps.
Once again this was done using the parametric analysis sweeping VSG from 0 to 5 V.
ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.
Layout on an NMOS
Nmos layout with pads and passing DRC.
NMOS layout vs schematic net list matched.
PMOS layout with bonding pads.
PMOS passing DRC
Lyout vs schematic matching.
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