Lab 3 - EE 421L 

Cesar Macias

maciasc4@unlv.nevada.edu      

9-28-2014

PRE LAB:

Tutorial 1

 We first created a voltage divider

 We then created a symbol four our volatage divider

We then created a n-well 10k resistor

Using the Mosis process we know that the sheet resistance of the procress is 800 ohms per square. If we need a 10K resistors, 10K/800=12.5 squares needed. The Mosis process tell us that the minumium width of the n-well should be 10 lambda, so we picked 15 lamba. Lamba is .3 um, so thewidth is 4.5 microns. To get 12.5 squares we need a length of 56.25 but that would not be within DRC rules, therefore we would make the length 56.1 microns which is the closest number to 56.25 within the layout rules.

 And extracted it.

LAB:

Using the 10K n-well resistor we created a new DAC. To do that we used the n-well resistor and re-created the R-2R piece. We stacked the resistors, and added connections between them through metal 1 in the n-taps. We then labeled those connections with the same name as they had in the schematic.

We DRC'd the design and after fixing all the design errors we extracted the layout. Once we had the extracted layout we ran the LVS to check for matching of netlist between the schematics versus the layout.

Once the netlist matched, we layed out out new DAC. This will be similar to the one previously layed out in lab 2. The pins and connections were inserted through layer metal 1 and the nodes were named the same as in lab 2 (B9, B8, B7...)

Once layed out, we DRC the layout and extract it.

Once extracted we can run the LVS complete the DAC once the net0list match.

For a .zip of lab 3 click here

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