Lab

Lab 2 - EE 421L

Cesar Macias

maciasc4@unlv.nevada.edu

9-18-2014

Design of a 10-bit digital-to-analog converter (DAC)

PRELAB
For this prelab we just imported the files given to us in the Lab 2 folder and simulated the ADC-DAC coverter.

ADC-DAC converter schematic

Simulation response of the above schematic

From the simulation results above one can see that the input, which is is sinusodial signal, is the same as the output except the output seems to be broken in many little pieces. This is because when the input entered the ADC, it got translated into a binary value. When the ADC sends the binary sequence to the DAC, the DAC outputs a value depending on the binary sequence received. This value is determined the the equation for the LSB. LSB=VDD/2^n where n is the binary postion incoming into the DAC.

So if we were only sending a "1" into b0 then the output will be VDD/2^1,
then if we were only sending a signal through b1 the output will become VDD/2^2 or VDD/4. B2 will be VDD/8 and so on. So depending on the sequence sent out, output will be b0+b1+b2+...+bn

LAB
for the lab we will create our own DAC following the picture above.
Below is our main piece, a 2R-R divider

We then made a symbol of the above piece. (seen below)

We then connected the pieces

And create a symbol for it

We then connect it to the ADC and test it once again.

To determine the total resistance of the DAC one can perform thevenin and superposition to realize that the total resistance of the circuit is R.

If the DAC drives a 10 pF load, one can see the delay, 0.7RC is about 75ns.

If the circuit drives only a 10K load and no capacitors, the 10K load creates a 4-1 voltage divides as seen below and the response is immediate. Input is 5 V output becomes 1.25 V

If the DAC has a 10K load and a 10pF load the output becomes a combination of both of the above outputs, it will have a 4-1 divider with a .7RC delay of about 44 ns.

back up proof

Retrun to labs