Project - ECE 421L
| F0 | F1 | Operation |
| 0 | 0 | Addition |
| 0 | 1 | Subtraction |
| 1 | 0 | AND |
| 1 | 1 | OR |
Most of the components of the ALU have been created in the previous labs, so now it will be a task of assembling the ALU. 2 8-bit 2 to 1 MUXs will be used to select either the output from A or B, A and B, or the output from the 8 bit full adder. The 8-bit full adder performs either addition by inputting A, B, and Cin=0, or subtraction by inputting A, B', and Cin=1. This setup is accomplished by inputting the F1 control signal into both the Cin for the full adder as well as using it for a control signal for the 8-bit MUXs (thus selecting B' for each input into the full adder). It is observed that this setup essentially takes the 2's complement of B (B is inverted and Cin=1 essentially adds 1). The schematic is constructed as shown below.
| A | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 |
| B | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 |
| F0 | F1 | Operation | ||||||||
| 0 | 0 | A + B | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | A - B | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | A AND B | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | A OR B | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
Part 2 - Layout of the ALU
To reduce the complication of the 8 bit ALU layout, we first create a 1-Bit ALU schematic and make a layout of the 1-Bit to verify that it LVS.
1 Bit ALU Schematic
1 Bit ALU Layout and LVS Result
