Lab 7 - ECE 421L 

Authored by Hongzhong Li,

Email: lih12@unlv.nevada.edu    

Today's date: 10/25/2014

Using buses and arrays in the design of word inverters, muxes, and high-speed adders


  

Lab description

In this lab I will explore arrays, busses, and I will layout an 8-bit adder. I will create logic gates including inverter, AND, NAND, OR, & NOR. and test their functionality with array and busses. Also, I will create a 2 to 1 demux and an 8-bit 2 to 1 demux.

 

Pre - Lab Work

 

Using MobaXTerm log into csimcluster.ee.unlv.edu. 

First we back up all our work from lab7 folder by downloading the file from the CMOSedu directory.Then email the file to our own email

 

   

Drafting schematic and symbol for the 4-bit Inverter

 

Using the inverter from previous lab, create the following schematic. Go to the inverter's property and change the instance name to I0 <3:0>, this will create 4 inputs and ouputs. Press shift+W to make bus connections to the inverter.

 

 


Symbol

 

pic1

  

Schematic for simulation

 

pic2

 

Simulation

 Note that the outputs drive different capacitive loads, and that the inverter does not function very well with large capacitive loads since the shapes become more curvy instead of rectangular.

 

 

Drafting schematic and symbol for an 8-bit input/output array of: inverter, NAND, NOR, AND,and OR gates.

 

8-bit Inverter schematic

 

 

Symbol

 

  

Schematic for simulation

 

 

Simulation

 

8-bit NAND gate schematic

 

pic

 

Symbol

 

pic3

  

8-bit NOR gate schematic

 

pic

 

Symbol

 

pic3

  

8-bit AND gate schematic

 

pic

 

Symbol

 

pic3

 

8-bit OR gate schematic

 

pic

 

Symbol

 

pic3

Simulation using 8-bit NAND, NOR, AND, and OR gates

 

 

Drafting schematic and symbol for an 2 to 1 MUX/DEMUX and its 8-bit version.

schematic of a 2-to-1 MUX

 

 
Symbol
 


Simulation
 

8-bit MUX 

8-bit DEMUX

Drafting schematic,symbol, and layout for an 8-bit Full Adder.

Fig12.20 8-bit Full Adder Schematic


Symbol

 

 

8-bit Full Adder Schematic using arrays and busses

 

pic

 

Schematic for Simulation


pic

 

Simulation

 

 

 

 

Next the 8-bit full adder was layed out. I began by laying a 1-bit full adder and connecting it with the 1-bit full adder schematic. 

 

  

 

LVS Result

 

This ends lab 7. We've covered all of the basic building blocks used in an ALU.

 

I back up my work as shown below.

 

 

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