Lab 5 - ECE 421L
Authored
by Hongzhong Li
Today's
date : 10/11/2014
Email: lih12@unlv.nevada.edu
Simulation of inverters using NMOS and PMOS
Lab
description
In
this lab we will layout two inverters. One will utilize a 20/2 pmos and
a 10/2 nmos, and the other will utilize a 100/2 pmos (set up as 5 20/2
pmos in parallel) and a 50/2 nmos (set up as 5 10/2 nmos in parallel).
After we have created the inverters we will simulate their
functionality with different capacitive loads.
Pre-Lab work
Using MobaXTerm log onto csimcluster.ee.unlv.edu
First we back up all our work from lab5 folder by downloading the file from the CMOSedu directory. Then email the file to our own email.
Drafting schematics, layouts, and symbols for the two inverters
After going through tutorial 3 we should have the following schematics and symbols created for:
- 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
- 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET)
We will now create a layout for the inverters above. From library manager,go to file -> New -> Cell View ->(layout) . Instantiate the nmos and pmos from NCSU_TechLib_ami06. Rember to use 12u for the pmos and 6u for the nmos.
Make sure to name the power and ground (vdd! and gnd! to match the
schematic pin names) Include "!" to indicate that its a global value.
DRC for design errors then extract and LVS. You should have something similar to the image below.
LVS Result for 12u/6u Inverter
LVS Result for 48u/24u Inverter
We can now create the schematics to simulate our inverters when driving a 100fF, 1 pF, 10 pF, and 100 pF capacitive load.
12u/6u Inverter driving a 1pF Load (Note: change the value of the capacitor accordingly)
48u/24u Inverter driving a 100fF Load (Note: change the value of the capacitor accordingly)
Simulation result -100fF
12u/6u Inverter
48u/24u Inverter
Simulation result -1pF
12u/6u Inverter
48u/24u Inverter
Simulation result -10pF
12u/6u Inverter
48u/24u Inverter
Simulation result -100pF
12u/6u Inverter
48u/24u Inverter
From
the simulation results, we can conclude that as capacitance increased,
the time it takes for output voltage to change is increased as well.
The 48u/24u inverter yields the similar result with a slightly faster
responding time.
UltraSim Results
Now we will repeat the last few simulations using UltraSim instead of Spectre. Launch ADE-L and go to setup->simulator/directory/host and select UltraSim from the drop down menu instead of Spectre. Remeber to include the stand alone model libraries.
Simulation result -100fF
12u/6u Inverter
48u/24u Inverter
Simulation result -1pF
12u/6u Inverter
48u/24u Inverter
Simulation result -10pF
12u/6u Inverter
48u/24u Inverter
Simulation result -100pF
12u/6u Inverter
48u/24u Inverter
The completed lab5 file can be downloaded from here.
This concludes the lab work. I back up my work as shown below.
Return to EE 421L Labs