Lab 3 - ECE 421L
Layout of a 10-bit DAC
In this lab we will layout the 10-bit digital to analog converter that we drew the schematic for in lab 2.
Pre-lab work
Using MobaXTerm log onto csimcluster.ee.unlv.edu
Launch Virtuoso from the /CMOSedu directory.
Go to File -> Library and make a new library called "lab3". Make sure to define the new library in your cds.lib file in the CMOSedu directory.
After we finished tutorial 1 we should have the following divider symbol created.
Check and and Save the symbol with the following schematic. Launch ADE L and load the state. Run the simulation and verify that the divider work as intended.
Shown below is the resistor created from tutorial 1.
Now we can begin the create the layout.
We look up the information from the MOSIS C5 process and discover that the sheet resistance is approximately 800 ohms. The desired resistance value is 10k. We can compute the value of the resistor as a function of the dimensions of length, width, and the sheet resistance of the process.
The width is
chosen to be 4.5um to match the ntap's dimension therefore that leaves
the length to be 56 um.
Namely Resistance = Sheet Resistance * (Length / Width).
Therefore according to the calculation, [800*(56/4.5) is approximately 10k] The length is adjust to 56.1 to ensure that the corner of the n-well resisotr is snapped to the y-axis grid. Since the X and y spacing is 0.15micron by default and 56.1/0.15 give us a integer), so we won't get any "edge not on grid" error.
Apply res_id on the n-well resistor layout , DRC and then extracted. Go to extracted view of the n-well resistor and we verify that the value is 10,21k which is close to the 10k value we desired.
Following Tutorial 1, we instantiate two 10k n-well resistors and connect them with metal 1. Then create input, outut, and ground pins around the metal 1. DRC and Extract the layout.
Finally LVS to get familiar with the process so we can go ahead to layout our 10-bit DAC using the 10k n-well resistor we created earlier.
The finaly layout should looks like the following, DRC, Extract, and LVS the layout to verify everything works.
The completed lab3 file can be downloaded from here.
Back up file
Make sure to back up your work by downloading the lab3 folder from CMOSedu directory. You can then email the file to yourself or upload it to googledrive, etc.