Lab 2 - ECE 421L 

Authored by Hongzhong Li,

lih12@unlv.nevada.edu

Today's date 09/18/2014

Lab description:

In this lab we will design a 10-bit DAC using an n-well resistance of 10k and compare its functionality to an ideal DAC.  Further, we will attempt to predict the delay the DAC has driving a 10pF load. Lastly, we will try to compare the functionality of our DAC driving a 10k load to one driving to the ideal DAC.

Create a new folder in CMOSedu named lab2. Unzip the file and upload the contents to lab2. Add DEFINE lab2 $HOME/CMOSedu/labl2  to your cds.lb file. Go to your CMOSedu directory and Launch Virtuoso.

Open the schematic called "Sim_Ideal _ADC_DAC"

 

Run the simulation (Launch the ADE, Session -> Load State -> Cellview -> OK, press the green start button) to get the following

We see that the output has lost precision from input. This occurs because when the signal is converted to a digital signal, it is only able to store with precision equal to the voltage range of its least significant bit. Note that when we design the DAC for the lab we will determine the voltage with VDD/2^n, where n is the number of bits.

Lab 2 - Design and Simulation of DAC:

From the Library manager go to file->new->cell view. Create a new cell view schematic called R2R. This will be your 1-bit DAC. It should be similar to the layout below. Use 10K resistors only.

Go to your copy of the 10 bit DAC and modify it. Replace all the 1bit DAC with the ones just created. 

The new circuit schematic and symbol should be similar to the images below.

Go to Create -> Cellview ->From Cellview and choose Symbol to create a symbol that looks like below.

 
Go to your copy of Ideal_ADC_DAC and replace the DAC with your own DAC design then run simulation to verify the deisgn,


 
 Simulation Result verified that it works with our own design.

 
To determine the output resistance of DAC, we calculate the parallel and series resistance of each bit and we should get 2R || 2R = R and for the last bit we have 2R instead of R thus it becomes 2R || 2R = R  again.  So if we keep creating parallel combinations of resistors, the output resistance will be equal to R (10k in this particular design).

Next, to calculate the delay of the DAC driving a 10pF load we use 0.7RC = 0.7 *10k*10p = 70ns. We then simulate the schematic to verify our hand calculations.
 

 Simulation result shows that at 0.5 Vin (50ns) to 0.5 Vout (124ns) is approximately 74ns which matches our hand calculations.

Next we test to see what happens if DAC drives a 10k Load:

Simulation Result: Notice how the 10k resistive load reduce the output voltage by a factor of a half.

Next, we see what happens when the DAC drives a capacitive load of 10pF:

 Simulation Result:

Finally, we see what happens when the DAC drives a RC Load:

Simulation Results: Notice that the output is reduced by a factor of a half due to the resistive load and it is lagging the Vin due to the capcitive load.

When the switches of the DAC are implemented with MOSFETS, it is necessary that the resistance of the MOSFETS be small compared to the values of the resistor, else DAC will draw more current thus causing unintended voltage drops.

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