Lab 8 - ECE 421L 

Authored by, Vincent Ibanez, Gerald Lee, Chris Mikhael

Email: ibanez.troy.e@gmail.com, leeg28@unlv.nevada.edu, mikhaelc@unlv.nevada.edu

Today's date 11/30/2014

The image seen at the below of the page shows how the chip's pads correspond to the pins of the 40 pin DIP package we will receive from MOSIS. 

Layout:

• 30u/0.6u NMOS (3 pins, DN, GN, SN, connect the p+ body, B, of the NMOS to the chip's ground pin)
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• 30u/0.6u PMOS (4 pins, DP, GP, SP, and BP)
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• Inverter made using 30u/0.6u NMOS and 60u/0.6u PMOS (3 pins, in, out, VDD_inv)
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• 61 stage ring oscillator using 6u/0.6u MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
• Shown below is the 6u/0.6u inverter used for each stage of the oscillator
  
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• Show below is the 61-stage ring oscillator. Note the Metal2 strip on the middle of the oscillator. It is used to loop the output of the last stage of the oscillator to the input of the first stage.
  
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• 20k n-well resistor (2 pins)
• L/W Ratio used is 90/3.6. The calculated resistance is 20200 Ohms.
  
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• 20k hi-res poly resistor (2 pins)
• L/W Ratio used is 22.8/1.2. The calculated resistance is 19703 Ohms.
• Note that the hi-res block used overlaps the poly2 layer.
  
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• 1k n+ resistor (2 pins)
• L/W Ratio used is 21.3/1.8. The calculated resistance is 986.9 Ohms.
• Note that we used a NoDRC layer over the N+ resistor to override Cadence DRC checks. Although there is resistance across the N+ well, Cadence picks it up as a short.
  
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• 1k p+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)
• L/W Ratio used is 25.5/2.7. The calculated resistance is 998.27 Ohms.
• Note that we used a NoDRC layer over the P+ resistor to override Cadence DRC checks. Although there is resistance across the P+ well Cadence picks it up as a short.
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• Bandgap reference (2 pins, VDD_bg and Vref)
• This design was the same design used in the EE421 Project. The components are compacted together in order to save layout space.
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• Overall
• We placed several rows and columns of NTAPS (3 of them) across the die to ensure that each components has a proper grounding.
• One node of the resistors are combined into a common node to save layout space (since components will be tested one at a time).
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How to test the following structures:

    Note: Some of the Pins on the resistors are shared. When testing using the following test structures, ensure that you are testing one circuit at a time. Also, before testing any of the components, make sure that you connect ground to 0V.

• 30u/0.6u NMOS (3 pins, DN, GN, SN, connect the p+ body, B, of the NMOS to the chip's ground pin)
• The NMOS observes the following pinout from the chip.
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• Connect DN (Pin 15) to 5V
• Connect GN (Pin 14) to 0V
• Check Voltage at SN (Pin 13), it should be 0V (OFF mode)
• Switch GN (Pin 14) from 0V to 5V
• Now SN (Pin 13) should read 5V (ON mode)

• 30u/0.6u PMOS (4 pins, DP, GP, SP, and BP)
• The PMOS observes the following pinout from the chip.
• 
  
• Connect SP (Pin 16) to 5V
• Connect GP (Pin 17) to 0V
• Connect BP (Pin 19) to 5V
  
• Check Voltage at DP (Pin 18), it should be 5V (ON mode)
• Switch GP (Pin 17) from 0V to 5V
• Now DP (Pin 18) should read 0V (OFF mode)

• Inverter made using 30u/0.6u NMOS and 60u/0.6u PMOS (3 pins, in, out, VDD_inv)
• The Inverter observes the following pinout from the chip.
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• Connect VDD_inv (Pin 22) to 5V
• Connect IN (Pin 20) to 0V
• Check Voltage at OUT (Pin 21), it should be 5V
• Switch IN (Pin 20) from 0V to 5V
• Now OUT (Pin 21) should read 0V

• 61 stage ring oscillator using 6u/0.6u MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
• The 61 stage ring oscillator observes the following pinout from the chip.
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• Connect VDD_osc (Pin 23) to 5V
• Using a oscilloscope, measure the frequency that from OSC_out (Pin 24)
• Frequency should be somewhere around 86.73Mhz (This frequency is derived using the MOSIS C5 Process)

• 20k n-well resistor (2 pins)
• The 20k n-well resistor observes the following pinout from the chip.
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• Measure the resistance between RES_com (Pin 25) and 20k_nwell (Pin 26)
• Resistance should be somewhere around 20k ohms

• 20k hi-res poly resistor (2 pins) 
• The 20k hi-res poly resistor observes the following pinout from the chip.
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• Measure the resistance between RES_com (Pin 25) and 20k_HiRes (Pin 27)
• Resistance should be somewhere around 20k ohms

• 1k N+ resistor (2 pins)
• The 1k N+ resistor observes the following pinout from the chip.
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• Measure the resistance between RES_com (Pin 25) and 1k N+ (Pin 28)
• Resistance should be somewhere around 1k ohm

• 1k P+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)
• The 1k P+ resistor observes the following pinout from the chip
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• Before measuring the resistance, ensure that you connect the 1k_P+_Well (N Well, Pin 30) to 5V
• Measure the resistance between RES_com (Pin 25) and 1k_P+ (Pin 29)
• Resistance should be somewhere around 1k ohm

• Bandgap reference (2 pins, VDD_bg and Vref)
• The Bandgap reference observes the following pinout from the chip.
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• Connect VDD_BG (Pin 31) to 5V
• Measure the voltage at Vref (Pin 32), it should read 1.25V
• Try to vary BG (Pin 31) a little bit, say from 4.5 to 5.5v
• The voltage at Vref (Pin 32) should stay at 1.25V
  

      
 
Finally, we backed up our design lab8ilm.zip directory and other files for future study.