Lab 6 - EE 421L 

Authored by Brian Kieatiwong

kieatiwo@unlv.nevada.edu

10/20/14 

Shown below is the schematic for a 2-input NAND gate.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/JCU7WF5U/Lab_6_A[1].JPG

Shown below is the symbol for a 2-input NAND gate with my initials labeled at the center.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/IZ7XHHOU/Lab_6_B[1].JPG

Shown below is the layout for a 2-input NAND gate.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/JCU7WF5U/Lab_6_C[1].JPG

The layout was then run through a DRC for verification.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/J2A0DM07/Lab_6_D[1].JPG

The layout was then run through an LVS for verification.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/FAJN4MKT/Lab_6_E[1].JPG

Shown below is the schematic for a 2-input XOR gate.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/IZ7XHHOU/Lab_6_F[1].JPG

Shown below is the symbol for a 2-input XOR gate with my initials labeled at the center.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/JCU7WF5U/Lab_6_G[1].JPG

Shown below is the example pulse statement schematic.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/J2A0DM07/Lab_6_K[1].JPG

Spectre was used to simulate the schematic with these parameters.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/FAJN4MKT/Lab_6_L[1].JPG

Below is the resulting graphs. These show glitches because different parts of the circuit have vaired time delays and are not perfect.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/IZ7XHHOU/Lab_6_M[1].JPG

Below shows the schematic of a full adder.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/JCU7WF5U/Lab_6_N[1].JPG

Below shows the symbol for the full adder.

file:///C:/Users/Brian/AppData/Local/Microsoft/Windows/Temporary%20Internet%20Files/Content.IE5/J2A0DM07/Lab_6_O[1].JPG



Be sure to zip all the files and save to an external hard drive. Files from this lab can be found here.

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