Lab 5 - EE 421L 

Authored by Brian Kieatiwong

kieatiwo@unlv.nevada.edu

10/13/14 

As described in the Tutorial 3, we will construct the inverter with the specified values. Below shows the schemtatic of the inverter.

The below figure shows the symbol of the inverter we just created.

The figure below shows the layout of the inverter we just created.

Once the layout is created, we DRC the layout and then proceed to extract the layout as seen below.

We will then implement the LVS function to ensure that the layout and schematic match.

Now, we will proceed to simulating the inverter symbols we have created using various capacitative loads. Below shows the schematic for 1pF.

We will be running a transient analysis to find the input and output voltages.

Below is the plot for a 1pF load.

Below is the plot for a 10pF load.

Below is the plot for a 100pF load.

Below is the plot for a 100fF load.

Be sure to zip all the files and save to an external hard drive. Files from this lab can be found here.

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