Lab 2 - EE 421L
Authored by Brian Kieatiwong
kieatiwo@unlv.nevada.edu
09/15/14
To begin, the file lab2.zip was downloaded and unzipped on the server running Cadence.
The following statement in line 65 was added to the cds.lib in the design directory.
Here, it can be seen that this library has been successfully added.
The following shows the schematic view of the cell sim_Ideal_ADC_DAC.
The
following shows the simulation of the cell sim_Ideal_ADC_DAC. The
background color, line thickness, and line type were manipulated to
offer better visuals.
The following topology will be used for the remainder of Lab 2.
Be sure to copy all associated Lab 2 files into a backup folder of an external hard drive.
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