Lab 7 - ECE 421L
8 Bit Inverter:
We start by placing an inverter, from previous labs. We select the inverter and goto edit object properties. Goto instance name and change the name to I0 <7:0>. This creates 8 inverters, where we will have 8 inputs and 8 outputs. We then use wide wires or a bus to make connections. This action will be used for all remaining gates and components.
Here is the completed schematic:
And here is the corresponding symbol:
Now we can simulate it's function:
Notice that each bit is connected to different capacitor loads. This proves that the 8 bit inverter works.
8 Bit AND Gate:
Here is the completed symbol and schematic:
8 Bit NAND Gate:
Here is the completed symbol and schematic:
8 Bit OR Gate:
Here is the completed symbol and schematic:
8 Bit NOR Gate:
Here is the completed symbol and schematic:
Now that we have the 8 bit AND, NAND, OR, and NOR gates, we can verify with a simulation.
Using the following schematic, we can simulate these four 8 bit gates:
Here are the results:
We know that and AND gate will only give a high output when both A and B are high, and zero for everything else. The NAND gate will be an inverted AND. The OR gate will only give a low output when both A and B are low. The NOR will be an inverted OR. Knowing this, we can clearly see that each of these gates are performing correctly.
Our
next task is to create the 8 bit DEMUX/MUX component. A multiplexer is
a device that takes multiple inputs and outputs them onto one output.
This is accomplished by using a toggle to select which input will be
outputted. A demultiplexer is the opposite of a multiplexer, we will
have a single input and multiple outputs, a switch is used to toggle
between outputs. We will see this demonstrated in simulations.
8 bit MUX:
We first create a 1 one bit MUX, here is the completed symbol and schematic:
Now that we have a 1 bit MUX we can go ahead create an 8 bit version (just as we did with the previous gates).
Here is the completed symbol and schematic for an 8 bit MUX:
Now to verify with a simulation:
(Note that we will sample only three outputs from the simulation schematic).
Here are the results:
Notice that A is outputted when S is high, and B is outputted when S is low.
Using the MUX circuit, we can easily convert the MUX into a DEMUX. This is done by simply making A & B outputs and making Z an input.
Here is the schematic that we will use for this simulation:
Here are the results:
Notice that when S is high, Z equals A and when S is low, Z equals B.
8 Bit Full Adder:
Using the full adder from the previous lab, we create an 8 bit full adder. We start by placing the full adder part in a new schematic cell. We then change the instance name to I0 <0:7>. This creates an array of 8 full adders. We then add pins to the schematic. Note that it is crucial to properly label the buses. Cin and Cout are the only pins that need to one bit and we need to cascade these pins (cin, cout). For example, cout<0> goes to cin<1>, cout<1> goes to cin <2>, etc. Using the proper bus labels we can simulate this circuit. We can see this in the following schematic:
Here is the corresponding symbol:
Now lets make the layout for this schematic. This is done by placing cascading 8 one bit full adders.
Here is the completed layout:
It passes DRC!
It's a match!!!
Now to verify with a simulation.
We will test a couple of inputs to check that the 8 bit full adder functions correctly.
We will first add A=11111111 with B=00000000, and cin<0>=1. This outputs s<0:7> =0, but cout=1.The answer is 100000000. This is because the first initial cin was set high.
Now we do the same input except cin<0> = 0. We get s<0:7>=1, and cout=0. The answer is 011111111 (9 bits). Unlike the first test, our first cin initial cin is set to zero. In this case we are simply adding 11111111 with 00000000 and we get 011111111, where the zero at the end is the cout.
These two tests show that our 8 bit full adder can perform a basic adding function. It also shows that the cin's/cout's are carrying through the whole circuit correctly.
Now let's look at a different kind of full adder found in fig 12-20.
Here is the completed schematic:
Using this schematic we create a symbol, which we will use to create a new schematic that will be our 8 bit version.
Here is the completed 8 bit symbol and schematic:
After completing this schematic and symbol, we now create an 8 bit layout:
DRC Passes!
Right view:
LVS Matches!
We now verify that our full adder functions correctly:
Note that the bits are labeled backwards. S<7> is the smallest bit and S<0> is the largest. So we test 11111111+1011. We should get100001010
Here is the simulation to verify this:
Again note that the in this sim cout is the greatest bit and s<7> is the smallest. Knowing this we can see 100001010. The full adder works!
This new version of a full adder (fig. 12.20) is important to know. The advantage of this version is it's speed. This is the circuit that is used in industry.
THIS CONCLUDES LAB 7. We know how to make the basic components that will be used to create an 8 bit ALU for the project.
