NAND Gate:
Using 6u/.6u NMOS and PMOS parts we construct the NAND gate. Here is what the completed schematic should look like:
Lab 6 - ECE 421L
Remember to assign the proper pin names.
Once we have the schematic we can then create a symbol
Note that we are using the common symbol for a NAND gate. For this symbol we used line segments, arcs, and circles.
Based on the schematic, we assemble the layout.
Be sure to that the frame of the layout is sized correctly. When we place this layout into another cell, we need to make sure that the terminals reach the end of the frame. We also want the frame height for all gates (NAND and XOR) to be the same. This makes future layouts look nicer and easier to connect. Also, make sure that all layouts pass DRC.
Now we create the extract cell and perform LVS:
It's a match!
XOR Gate:
Again we use 6u/.6u transistors for this circuit. Here is the completed schematic:
Notice that we used labels instead of wires for the connects of A, B, Ai, and Bi. This helps to make the schematic look cleaner.
Next we save and check and then we create a symbol.
Again we use the common symbol for an XOR gate.
Using the schematic as a reference we assemble the layout (ensure DRC passes).
Next we perform the LVS test.
It's a match!!
Simulations of the NAND & XOR Gates:
We construct the following schematic to simulate these two gates. Note that we will use the SPECTRE simulator.
For this to work correctly we assign V1 (A input) a period of 400ns and V2 (B) a period of 200ns.
This will give us the correct test inputs. Here are the truth tables that we will reference:
XOR GATE:
NAND GATE:
Here are the simulation results:
As we can see the gates are correct!
Creating The Full Adder:
Now that we have the NAND and XOR gates, we can now start making the full adder (FA).
Here is the completed schematic of the full adder:
Notice that we create pins for a, b, and cin inputs. And s (sum) and cout outputs.
Here is the symbol that we will use for future labs:
For the layout, we use the layouts of the XOR and NAND gate (as instances). We also use the schematic to make the proper connections. And again ensure DRC passes. Here is the completed layout:
Notice that it is a rather large layout, and much more complicated. The goal is to create a very clean and organized layout. Notice that all connections are made between the vdd and gnd contacts (all kept inside). To prevent any DRC errors and promote clear routing, we use metal 1 for horizontal routes, metal 2 for vertical routes, and metal 3 for horizontal routes. This technique ensures that there are no obstructions (no dead ends). For convenience, all the inputs are on the left and outputs on the right. We also included two additional large taps (ptap/ntap) for gnd and vdd. This is not required but, it makes external connections easier and it makes the layout look cleaner and more uniform. It also promotes a nice cell frame for future labs/projects. Finally, notice that all inputs and outputs are made on metal 1.
DRC passes (Left close up view):
LVS Matches:
Right view close out of layout:
Middle close up view:
Full Adder Simulation:
Now we simulate our full adder to ensure proper functions.
We will reference the following truth table:
Note that we will use SPECTRE to simulate. Based on the truth table we will have three voltage sources for a,b, and cin inputs. Input b will have a period half of a, and cin will have a period half of b.
Here is the simulation schematic:
Here are the simulation results:
Reviewing the truth table, we see that our full adder functions correctly!!!
THIS
CONCLUDES LAB 6. We now have fully functioning NAND & XOR gates, as
well as a full adder. The schematics/symbols and layouts for each of
these components will be used for future labs/projects.
