Lab 5 - ECE 421L
For this lab we will learn how to design inverters using PMOS and NMOS transistors. Specifically, we will create one a 12u/6u inverter (PMOS width=12 microns and NMOS width =6 microns, all lengths will be .6 microns) & one 48u/24u inverter (we will copy the 12u/6u schematic and then input a multiplier of 4 in the object properties window for the NMOS and PMOS). We will create a schematic, symbol and layout for the two inverters. Finally, using the symbols for each type of inverter, we will simulate (using UltraSim transient) them driving various capacitive loads: 100 fF, 1 pF, 10 pF, and 100 pF.
Creating the 12u/6u Inverter:
First we will create a new cell called 12u6u_inverter. Open the schematic and lay down one 4 terminal NMOS and one 4 terminal PMOS. Be sure that the NMOS has W= 6u and L=600n & that the PMOS as W=12u and L=600n.
Here is the completed schematic:
Be sure to connect vdd at the top and gnd at the bottom. Connect both gates together and assign a pin name called "A" (input type).
Next connect the PMOS and NMOS drains together and assign pin name called "Ai" (output type). Finally, connect the NMOS bulk to gnd and PMOS bulk to vdd.
Note that we we need to use the correct models for the PMOS and NMOS (ami06N & ami06P).
Then we create a symbol view:
Clicking Edit we can draw lines and circles. Using the grid we create a symmetrical triangle that is appropriately sized.
Be sure to label your inverter symbol.
Finally we create the layout. Create a new layout view in the same cell and lay down a NMOS and PMOS transistor. Make sure to use the same widths/lengths as the transistors found in the schematic.
Here is the completed layout:
Place a ptap (2 rows/4 columns) connector below the NMOS. Using metal 1, connect the ptap to the NMOS source (left terminal). Place a ntap (2 rows/4 columns) connector above the PMOS. Using metal1, connect the ntap to the PMOS source (left terminal). Connect the two drains together using metal 1. Finally, connect the two gates together using poly and then terminate to a poly_metal1 contact. Assign the appropriate pin names: "gnd!" on the ptap contact using metal1, "vdd!" on the ntap using metal1, "Ai" on the drain using metal1, and "Ai"on the poly_metal1 using metal1.
Perform a DRC check
Now let's verify LVS.
From the layout view, extract the layout. Open the new extract view from the library manager. Then perform the LVS check.
IT'S A MATCH!
Creating the 48u/24u Inverter:
Copy the 12u6u_inverter cell and rename as 48u24u_inverter. Open the schematic and open the object properties window for both the NMOS and PMOS transistors. Input a 4 into the multiplier entry box. This will change the NMOS width to 24 microns and the PMOS width to 48 microns, hence the name 48u/24u.
Here is what your new schematic should like:
Notice the blue circles...m=4 is the multiplier.
Using the same symbol shape, we change the name to 48u/24u:
Open the layout view and change the multiplier to 4, for both the PMOS and NMOS.This will create a 48u PMOS and 24u NMOS. Next increase the size of the ntap and ptap. Both should have 8 columns.
Here is the completed layout:
Connect all the gates, using poly, together. Connect the drains together using metal1. Connect the three source of the NMOS to the ptap using metal1. Connect the three sources of the PMOS to the ntap using metal1. Finally, connect all the gates (four finger) together using poly, and then terminate to the four column poly_metal1 contact. Same as the 12u/6u layout, assign the same pin names.
Now to verify LVS.
As done before, create an extracted view and open it. Run LVS.
IT'S A MATCH!!
Now lets observe and compare how these two inverters drive various capacitors. Note that we will use the UltraSim simulator to perform simply transient analysis. Be sure to select the correct models (AMI06N and AMI06P).
Simulating the 100fF Load:
These two sims look similar, except that the larger inverter (48u/24u) appears to have a little less delay.
Simulating the 1pF Load:
12u/6u Inverter:
48u/24u
Comparing the 1pF load with the 100fF load, we can see that the time delay has approximately doubled. Comparing the two inverters with the 1pF load, we see that the larger inverter responds much faster. By reading the graph, the smaller inverter has a time delay of approximately 5ns and the larger inverter has a time delay of approximately3.5ns.
Simulating the 10pF Load:
12u/6u Inverter:
Comparing this sim with the 100fF load, we can see that the time delay has increased significantly. Approximately by a factor of 10. Comparing the two inverters with the 10pF load, we can see that larger inverter responds much faster than the smaller inverter. The smaller inverter would not be recommended for driving a 10pF load, especially for digital circuits.
Simulating the 100pF Load:
12u/6u Inverter:
48u/24u Inverter:
Comparing this load with the other loads we can see that the delay has increased greatly. The larger inverter is still faster then the smaller one.
In general we can see that increasing the width of an inverter can greatly improve it's performance, by reducing the time delay.
THIS CONCLUDES LAB 5.
WE NOW KNOW HOW TO PROPERLY DESIGN VARIOUS SIZED INVERTERS; CREATING SCHEMATICS, SYMBOLS, AND LAYOUTS. AND FINALLY TO VERIFY THEIR PERFORMANCE.
