Lab 3 - ECE 421L 

Authored by Michael Kajkowski,

9/17/2014

kajkowsk@unlv.nevada.edu 

Introduction:
In this lab we will learn the basics of creating a layout. Using this knowledge we will then create a layout for the DAC circuit that we made in the previous lab. The first step will be to make a 10K n well resistor, then we will use this resistor (like a component) to build the 2R_R schematic. Note that because our DAC consists of 10 individual 2R_R symbols, we only need to make the layout for the one bit 2R_R schematic/symbol. The layout for this schematic/symbol will propagate through the entire DAC. 

Creating the 10K n well resistor:
Before we get started lets continue reading through tutorial 1. The rest of this tutorial will give us the knowledge needed to create the n well resistor layout. After doing so, we will go into library manager and create two new cells. Located inside the same library as the previous lab, we will create a layout view for 2R_R & a layout cell named R_nwell_10k. The R_nwell_10k cell will be our component that we will use later on. 

First, open the R_nwell_10k cell and select n well in the Layer Selection Window (LSW). Then hit R on the keyboard and draw any shaped rectangle. Note that our n well should be 4.5 um wide and 56 um long. We will discuss these dimensions in more detail later on in this lab. Once you have drawn this rectangle, you will then click inside the rectangle and hit Q to change properties. A window will appear and you will need to input -28 into “left”, 28 into “right, -2.25 into “bottom” and 2.25 into “top”. Then hit OK. Here is what you should get:

 Notice how the rectangle's dimensions changed.

 To verify that we satisfy the design rules, go to Verify=> DRC. A window will appear, hit OK and watch for any errors. If your n well did not pass the DRC then error messages will appear. Generally because we are using the C5 process our minimum width of n well should be at least 3.6 um. In our case our width is 4.5 um, so we should expect no errors in this regard. However we do find four errors. Reading these errors (in the CIW window) we learn that the edges of the n well are not on the grid. To fix this we need to slightly modify our dimensions, so that our n well will snap to the grid. First we need to kit E on the keyboard. A window will appear and you can then see what that the Snap Spacing is set to .15 um.

 Using this information, we can simply divide our width and length by .15 um.  Here’s what we see, 4.5/.15=30 & 56/.15=373.33333. We can see that 56/.15 is an irrational number; this is the root of our problem. To correct this we can simply add .1 to 56. Click the rectangle and hit Q. 

Here is what you should input:

 Perform a DRC check once again and you should receive no errors.

 Now that our n well passes DRC we can now add connections to our resistor. 

Hit I and select the ntap component as seen below:

 Make sure to select 2 rows of contacts. Place the ntap’s at the right and left ends of the n well.
Be sure to hit shift E and the layer editor options window will appear. Make sure to de-select “Gravity On”. Next hit E and the display options window will appear. Make sure “Pin Names” is checked and change the “Stop” entry from zero to 10. Hit OK

Now we can give these connectors pin names.
 
Select metal 1 in the LSW and goto Create=>Pin. Zoom in to the right connector and draw a rectangle matching the size of the box as seen below.  Then position the label in the center. Make sure to name the pin in the Terminal Name box & select the correct I/O type.

Perform the same procedure for the left side.
 
Next select res_id in LSW and draw a rectangle over the n well (excluding the connectors).
Then save and perform a DRC, there should be no errors.

 Here is what you resistor should look like:

 Finally, we need to verify that our resistor is 10k ohms. Goto Verify=> Extract and then hit OK. Goto library manger and go to the R_nwell_10k cell. You will notice that there is a new view called extracted. Open the extracted view. Here is what you will see:

We can see that the resistance is approximately 10K ohms. (Note that the MK Extract is just a label to personalize my view). 

 We now have a 10K n well resistor!!!

Creating the 2R_R Layout:
Open you newly created 2R_R layout view. Hit I and find your 10K n well. Place three of them onto the layout (stacking them on top of each other with some spacing between them). You will have to space them as close as possible without violating DRC rules. For this process the minimum spacing is 12 lambdas. Here’s what your completed layout should look like:

As seen above, use metal 1 to draw rectangles to connect the resistor connectors.  Further, as done before, create pin names ( left, top, and bot) to match the labels seen in the 2R_R schematic. Remember that the left pin is an input and the other two are in/out type of terminals.

Perform a DRC check and extract the layout.
   
Now we are ready to perform a LVS check (this ensures that the layout matches the schematic).
Open the extracted view and goto Verify=>LVS.
Here is what you will see:

Click run or outputs to verify.

Here is what you will see when you hit Run

Here is what you will see when you hit output:

This output shows that the LVS passed, but it provides more detail.

 We have successfully created a layout for our one bit DAC schematic, which has propagated through the entire 10 bit DAC cell.

   
Discussion Points:
One important point to discuss is how we determined which dimensions to use for the n well resistor.  We know that, according to the C5 MOSIS process, the resistance per unit square for n well is 800, lambda=300nm, and the allowed minimum width of n well is 12 lambdas. We also know that we want to achieve a resistance of 10K ohms.
   
Knowing these things we can determine our dimensions. For this lab we arbitrarily decided our width to be 15 lambdas. We then calculate our length:    10k=800(length/15) =>  length= 187.5 lambdas. So the dimensions are Length=187.5*300nm=56 microns & Width=15*300nm=4.5 microns. To verify our dimensions and resistance, cadence allows us to create a ruler (hit k on keyboard) to measure the dimensions and while in the extraction view, as seen before, we can visibly see the actual resistance of the n well.

Here is the measured dimensions for our n well resistor:

 As you can see the dimensions match our calculated results.

 Furthermore, we can verify that our well spacing is acceptable with the C5 MOSIS process:

Notice that each space is greater than the 5.4 micron minimum requirement (18 lambda => 18*300nm=5.4 microns).

 And here is our final DRC check of our 2R_R layout:

 Here is our final DRC check for the extracted view:

This concludes the lab.

In this lab we covered the basic procedures for creating a layout.

Here is my lab 3 directory: mk_lab3.zip 

MAKE SURE TO BACK UP ALL OF YOUR LAB 3 CONTENTS 

(zip and email your work to yourself).

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