Lab

Lab 2 - ECE 421L

Authored by Michael Kajkowski,

9/8/2014

For this lab we will be building a 10 bit Digital to Analog Converter (DAC). The DAC will consist of only 10K resistors.

We will cover basic design techniques for schematic and symbol construction and we will verify our results using

SPECTRE simulations. For example, our sims will verify that the 10bit ADC_DAC circuit is correct and the time delay

of our 10bit DAC.

Prelab Work:

Upload and unzip the lab2.zip file into your home directory. This directory will consist a couple useful cells that will make

the work easier. Make sure to add DEFINE lab2 $HOME/CMOSedu/lab2. Once you have done this, start Cadence and open up

the Library Manager. Look for the sim_ideal_ADC_DAC cell (found under lab2).

Open the schematic cell. The cell will contain the following:

Then, double click spectre_state 1 (found under the same cell). The ADE-L simulator will appear. Hit the green button.

The sim should run and you will see Vin and Vout plotted. We can change the color of the background and of the traces.

First hit Q and then select the color of your choice, we will use white for this lab.

To change the style and color of the Trace, click the trace and then hit Q.

Here is what the sim should look like:

Notice that with the thick solid lines and white background it is much easy to read the graph. This will come in handy for future labs.

Lab Work:

Here is the model that we want to create for the 10 bit DAC:

The model is only for 5 bits, we will need to add the 5 extra bits to it in Cadence.

In the library manager, copy the sim_Ideal_ADA_DAC & Ideal_10-bit_DAC cells

After this you will want to open the copied 10bit DAC schematic and delete everything in it. Then create a new cell called 2R_R.

Within the 2R_R schematic you will need to create the following schematic:

Be sure to label the three terminal points with pins. (The left pin is an input and the top and bot pins are in/out signals).

Next goto create and create a symbol for this circuit.

This is the symbol that should pop up.

Next open the copied 10bit DAC schematic and plot 10 of the 2R_R symbols using instance and component. Connect

each of the 2R_R symbols like you would with regular components using wires. Here is what you should have:

You will not need to draw a symbol from sketch because this copied file already has a symbol

associated with it. The only thing you need to is change the name of the 10 bit DAC symbol and make sure your pins match the

symbol pins.

Here is an example of what your DAC symbol should look like:

Finally, open your copied sim_Ideal_ADC_DAC schematic. Select the DAC symbol and delete it.

Then using instance and component, select your DAC symbol and place it in the same spot.

Here is the completed ADC_DAC circuit:

We can now simulate the completed circuit and verify that it is correct.
Here is the result that we got:

Comparing this sim with the original sim, we can see that our completed DAC circuit was correct.

We can examine what happens when we introduce an R, C, and R/C load to the ADC_DAC circuit.

Here's the circuit and sim with a 10K resistor load:

Notice that the amplitude for Vout dropped to 2.5V. This is due to the fact that the output resistance is 10K ohms and by placing the

10K load we get half the input voltage at Vout (voltage division=> Vin[R/(R+R)]=Vin/2=Vout).

Let's try a capacitor load of 10pF:

We can see that the 10pF cap load brought the Vout signal to be out of phase with Vin. This time delay will be

examined more closely later in this lab. Further, we can see that the cap seemed to have greatly smoothed out the Vout signal.

Now lets see what happens with an R/C load (R=10k, C=10pF):

Vout is out of phase with Vin.

Time Delay Analysis

For this section of the lab we took out DAC circuit and grounded all inputs, except B9, to ground. B9 will be set at VDD=5volts.

This input is the binary number 1000000000, which is 512. And our LSB=.00488 (LSB= 5volts/(2^10bits)=.00488). This means that

The analog representation for this digital number should be 2.5 volts (512x.00488=2.5). When we graph our RC curve we should

see the signal increase to 2.5 volts.

For this analysis we will use a 10pF cap. All that is left is to figure out the output resistance.

From the schematic you can easily determine the output resistance. Starting from the bottom, or at ground,
Notice that you have two 10k resistors in series & in parallel with two others. These can be written as two 20k's in parallel.
From circuit theory we know that the resistance will be half, if the two resistors in parallel are equal value.
Therefore the resistance of these two resistors is 10k. This 10k will be added in series with the 10k above it, giving you 20k.
Again, you will have 20k in parallel with 20k. As you move up the schematic, adding the resistors up, you will see that
the total output resistance will be 10k. Also note that if you were to drive a 10k resistive load (as seen previously),
you will have an output voltage that will be half of the input voltage. We know that in a voltage divider,

if you were to divide a voltage among two equal valued resistors in parallel, you will yield half of the input voltage at the output.

Which was demonstrated before.

Now that we have both C and R, we can calculate the time delay.

Time delay=.7RC-.7(10k)(10pF)=70ns

The verified result:

We can observe that the max. voltage is 2.5 volts, as predicted. Further, we can see that the time delay is approximately 70ns.

This is determined by looking at the point where we have half of 2.5, which is 1.25. At this voltage the time is around 74ns.

Our calculations are correct!

Food for Thought

Notice that in the 5 bit DAC circuit, from the beginning of the "lab work" section, we can see that there are switches

in the circuit. During the course of this lab we did not install switches. But if we did use the switches we would like to assume that

they contribute little to no resistance to the circuit. Specifically, we would want them to be much smaller than R.

If the switches were not small compared to R, we would have additional resistance added with the two 10K series resistors (for each bit).

As a result this would increase the total output resistance and cause a greater voltage drop of Vout.

This concludes LAB 2. We now have a working 10 bit DAC, verified with simulations!

BE SURE TO BACK UP ALL OF YOUR LAB CONTENTS!!

mk_lab2

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