Project - ECE 421L 

Authored by Michael Kajkowski,

11/5/2014 

Email: kajkowsk@unlv.nevada.edu

 For this project we will building an 8 bit ALU. Our ALU will include the following operations: AND, OR, ADDITION, & SUBTRACTION.
We will divide this project up into two main parts. For the first part, we will construct the schematic of the 8 bit ALU. We will finally verify with simulations. For the second part, we will construct the layout for our 8 bit ALU.
 
PART I:
   
 The strategy is to first build & simulate a 1 bit ALU schematic. Once we have a properly functioning 1 bit ALU, we will cascade 8 of them, giving us an 8 bit ALU.
   
Here is the completed 1 bit ALU:

Notice that we are using MUX's from lab 7. These MUX's allow us to select the operation function. For ADDITION (F1=0, F2=0), SUBTRACTION (F1=1, F2=0), AND (F1=1, F2=1), OR (F1=0, F2=1). Notice that for subtraction we will automatically set cin to high, so that we can properly perform the subtraction function.  We will be using 2's compliment for subtraction. From the schematic we can see that we will first invert B, then add it to A, and finally adding one to it. Typically, in 2's compliment subtraction we ignore the greatest extra bit (Cout). We will see this in some simulations.
   
Here is the symbol for this schematic:

 
Now let's simulate the 1 bit ALU:
 
For this test we will test all four operations with all combinations of A and B (00, 01, 10, 11).
   
 
 Going through each combination of F1 and F2 we can  see that our ALU is working. For example, F1=0, F2=0 (ADD) and A=1, B=1, we can see Cout=1 and Z=0 (1+1=10), note that for all operations except subtraction we ignore cin=1 & we will ignore cout for all operations except ADD. Another example, F1=1, F2=1 (AND) and A=1, B=0, we can see Z=0. Let's look at OR, F1=0, F2=1 and A=0, B=1, we get Z=1. Final example, F1=1, F2=0 (SUB) and A=1, B=1, we can get Cout=1 and Z=0. (1-1=0), again note that in 2's compliment subtraction we would actually get 1-1=10, we would ignore the extra bit of 1. We can look at more combinations seen in the above simulation.
   
 Now that we have a 1 bit ALU, we can now build an 8 bit ALU.
   
 Using the symbol from the 1 bit ALU, we create an array (what we learned from lab 7) which will give us eight 1 bit ALU's. Our pins will include: A (8bits), B (8 bits), F1/F2 (2 bits), Cout (8 bits).  We will first load the F1 bit into Cin<0> and then Cout<0> into Cin<1>, Cout<1> into Cin<2>, etc. The F1 bit for subtraction will be 1, this loaded into the first Cin allows us to properly perform 2's compliment.
     
Here is the completed schematic:

   
 Now lets simulate.
   
Here is the schematic we will use to simulate:

We will set A and B at constant values and run through the four operations.
     
       
 A=10100001, B=10000001
 
As an example we can see for ADD (F1=0, F2=0), the output is 100100010 (9bits, which is correct). Let's try subtraction (F1=1, F2=0), the output is 00100000 (8 bits). For AND (F1=1, F2=1) the output is 10000001. For OR (01), the output is 10100001. Appears to be correct!
   
A=00000101, B=00000001

     For this example we have A=5 and B=1. From the simulation we can see ADD (Z=00000110=>8), SUB (Z=00000100=>4, again we ignore the cout), AND (Z=00000001, again we ignore the cout), & OR(Z=00000101, again we ignore cout)....Everything appears to correct!!
   
   
After examining these various tests, it appears that our 8 bit ALU is in working order!

PART II

   For this part we will create a layout for the 8 bit ALU schematic. The first step is to create a layout for the 1 bit ALU. Using the individual layouts for the AND, OR, MUX, INVERTER, & FULL ADDER as building blocks, we construct the 1 bit ALU.

  Notice that its passes DRC.   

Notice that it passes LVS.

Using this 1 bit ALU as a building block (using 8 of them), we can build the 8 bit ALU. We can see from the schematic that we need to to connect F1 into Cin<0> and then Cout<0> into Cin<1>, Cout<1> into Cout<2>, so on and so forth. Cascading the individual ALU's correctly is critical. We will create a bus, connecting all the F1's together. We do the same for F2. We will use Cout<7> as out final Cout output. The A and B inputs will be 8 bit inputs and the Z output will be have 8 bits. We will also create a metal 3 bus for vdd! and gnd!

Here is the completed layout:

Notice that it passes DRC!

Here is a close up of the top left corner:

Bottom left corner:

Bottom right corner:

By observation of the layout, we can see that all the individual terminals have been properly connected. We can also see that the appropriate pins names have been assigned. We can now check to see if this layout matches the 8 bit schematic.

By inspection of the extracted view, we can see that the layout passes LVS!! Furthermore, we can see that the total width of this 8 bit ALU is approximately 757 microns and the height is around 191 microns. The bond pad that we will use for lab 8 will be approximately 1500x1500 microns squared. It can be concluded that our 8 bit ALU is compact enough to fit comfortable on the bond pad.

THIS CONCLUDES THE EE 421L PROJECT. WE HAVE SUCCESFULLY DESIGNED A COMPACT 8 BIT ALU.

 
Here is my complete project directory (including referenced files): proj_mk.zip

     
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(zip and email your work to yourself).