Lab 3 - ECE 421L 

Authored by, Vincent Ibanez

Email: ibanez.troy.e@gmail.com

Today's date 09/22/2014

  

PreLab:

     
To layout the resistive divider, begin by making a new cell view for the layout of R_div.
1.png
    
Next go to the menu items Options -> Display (or just press e).
Set the display so that Pin Names are shown.
Change the Snap Modes to diagonal.
Note that the Display Levels has no depth, that is, the layout of a cell placed in another cell will show as an outline. To see the contents, we need to increase the Stop level. We'll do this later just so we can see this window again and what an outline of a cell looks like.
2.PNG
 
We then start the R_div cell layout by creating the R_n_well_10k cell that we are going to instantiate in the R_div cell layout.
In this cell (R_n_well_10k cell), let's start by creating a rectangle on the n_well layer for the 10k resistor.
The sheet resistance of the n-well in the C5 process is roughly 800 ohms.
The minimum width if n-well is 12 lambda (3.6 microns since lambda here is 300 nm) so let's make a 10k resistor using a width of 4.5um and a length 56 um.
However, the problem is that 56 um is not divisible by 0.15. In order to make it divisible, we need to increase the length to 56.1
3.PNG
   
Make sure to DRC check before we proceed and ensure that there are no errors.
4.PNG
   
Next let's add connections to the end of the resistors. Press i and navigate/select the NTAP (metal 1 connection to the n-well) as seen below.
Make sure that the columns is set to two.
5.PNG
   
Adding these connections to the ends, we get the following.
6.PNG
   
Set the depth to 10 by pressing E, to view the ntap layers.
7.PNG
   
Line them up to the N well resistor and DRC to ensure no errors.
8.PNG
   
Next add pins to the layout by adding a pin rectangle in the metal 1 layer, ensure that the "Display Pin Names" are checked. Name pin as follows.
9.PNG
10.PNG
 
Next we draw a resistor rectangle in the "res_id" layer that is the same size as the n_well. The image should look like the image on the bottom. DRC it as well.
11.PNG
   
Next we extract the layout to determine the resistance's value(and to see if the setups match the 800 ohms n-well sheet resistance we got from MOSIS). Go to Verify -> Extract.
Then we can open the extracted cell from the library manager. It should look like below. Zoom in to see that it is 10.21k.
12.PNG
   
We are now ready to draw the layout of the R_div cell.
Open the schematic view of the R_div cell (so we remember what is in it, like Pin Names).
Open the layout view for the R_div cell (nothing in it).
Instantiate two of the 10k n-well resistor layouts.
DRC the layout to ensure that the resistors are far enough apart.
13.PNG
     
Next we draw rectangles in the metal 1 layer to connect the resistors together as seen below. DRC to ensure no errors.
14.PNG
   
Next we add pins on the metal 1 layer named in, out and gnd as seen below. Ensure that pin names are set to display. Again, DRC to ensure no errors.
15.PNG
   
Extract the layout as mentioned before. Then LVS the layout by selecting Verify -> LVS and set the extracted view's cell name (here R_div) and that its view is extracted as seen below.
Hit Run and OK to "Save Cellviews" (if asked)
When the LVS is done it will tell you it has succeeded.
16.PNG
   
Unless, there is an error... rename gnd to gnd! to correct the error.
17.PNG
   
Rerun the LVS. Make sure it passes.
18.PNG
     
Finish the lab by backing up your files.
backup.PNG
   
Main Lab:

This lab focuses on the layout of the 10-bit DAC you designed and simulated in Lab 2   

A 10-b R2R DAC Layout Design

1. How to select the width and length of the N-well resistor.

 
The sheet resistance of the n-well in the C5 process is roughly 800 ohms based from the The MOSIS Data sheet.
The minimum width of n-well based on Submicron design rule of C5 process is 12 lambda (3.6 microns since lambda here is 300 nm) so let's make a 10k resistor using a width of 4.5um and a length 56 um. However, the problem is that 56 um is not divisible by 0.15. In order to make it divisible, we need to increase the length to 56.1

3.PNG

    
We can then obtain the extracted view to ensure that the resistor is around 10K ohms.

12.PNG

     

2. How to measure the width and length by Electric

Cadence provides the Ruler to help us the meaure. We setup the length above meaning the distance between two contacts(highlighted by the red pen as seen below). The width is highlighted by the blue pen.

rul_marked.PNG

     

3. Design the DAC Layout

Considering the minimum spacing between wells at different potential is 18lambda(5.4 microns), I redesign the R2R divider as seen below and create a P+ ring to reduce the noise. I also created pins on the metal 1 layer.

Minimum width of pactive is 2 microns so we extend path width to 2.1 to make it divisibile by 300nm. Nwell to Pactive spacing is also 4.5 microns.


bitelement.PNG

   

The following image is the R2R divider schematic using three 10k n-well resistors plotted in Cadence.

schematic2.PNG

     

As the basic circuit in the DAC, I verify the DRC and LVS without errors.

18.PNG

   

Next design the schematic of the DAC. From the lab 2 symbol for the DAC bit, we instantiate it into an another cell and create a column of 10 (for 10-bit conversion). Then connect them together with a bottom 10k resistor as seen below. Don't forget to add the input pins and the output pin.

 
schematic1.PNG
     

Now let's design the layout. Instantiate the layout cell for the DAC bit into a new cell and make a array having 10 columns. Don't forget to add one 10k N-well resistor on the bottom. Use metal1 to connect 10 numbers of output nodes, 1 output and 1 gnd. Notice that I use via1 and metal2 to connect all the gnd together. 

whole.PNG    

     

Here is the top part of the design.

top.PNG

     

Here is the bottom part of the design. The bottom 10k resistor is circled in red.

botres.PNG

       

Run final DRC and LVS to check no errors in this layout as shown below.

finalDRC.PNG

     

Finally, backup your design lab3 directory and other files for future study.


Return to labs