Lab 2 - ECE 421L 

Authored by, Vincent Ibanez

Email: ibanez.troy.e@gmail.com

Today's date 09/07/2014

PreLab:

• Download lab2.zip to your desktop.
• This archive contains a simulation example using an ideal 10-bit Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC).
• Upload this zip file to the design directory on the server that you are running Cadence from, e.g., Tutorial_1, CMOSedu, etc.
• Note that it's assumed you are using the NCSU Cadence Design Kits.

• Unzip this directory and add, to your cds.lib in the design directory, the following statement (assuming the design directory is CMOSedu): 
• DEFINE lab2 $HOME/CMOSedu/lab2

• Start Cadence from the design directory.
• Use the Library Manager and navigate to the lab2 Library as seen below.

• Open the schematic view of the cell sim_Ideal_ADC_DAC. 
• This cell contains the ideal 10-bit ADC and DAC as seen below.

• Run the simulation (Launch the ADE, Session -> Load State -> Cellview -> OK, press the green start button) to get the following.
• The next image shows the results of the simulation.

• In order to change the background color, we right click on an empty space in the graph, and click graph properties.

• We then select a white color as a background,.

• Now, the graph has a white background.,

• In order to change the line thickness and type of the traces, we right click the plotted signals on the left and select trace properties.

• We can then set the Type/Style so be a solid line, with a medium thickness, and do the same for the other signal.

• After the changes are made, the resulting waveforms are shown below.
  

• In this waveform results and looking at the circuit diagram, we can see that Vin is converted into digital signals(B[9:0]) by the analog-to-digital converter. These digital signals are then fed into a digital-to-analog converter and we can see the output waveform Vout. We can see that Vout is not as smooth as Vin and this is because of the resolution of both the ADC and DAC converters. The more bits that it has, the finer the resolution we can get.
• For instance let's compare the results of a 10 bit ADC_DAC converter vs. a 4 bit ADC_DAC converter.
• 10 bit ADC_DAC converter           
  

• 4 bit ADC_DAC converter

• The waveform of the 10bit ADC_DAC converter is smoother than the 4bit counterpart due to more bits = higher resolution.

• We can determine the the least significant bit (LSB, the minumum voltage change on the ADC's input to see a change in the digital codeB[9:0]) of the converter by using the equation, 

  1 LSB = VDD/2^n where n is the number of bits in the ADC, in the case where n=10 and VDD is 5 volts, this change is 4.88 mV. This means that in order for a signal change to propagate into the output, the input must be in multiples  of 4.88mV.

• Let us finish this up by backing everything into Dropbox.

1. The design of a 10-bit DAC using an n-well R of 10k
• From the lab 2 that has been downloaded previously, we need to convert that into a resistive DAC, we to this by first copying the design that we already have and modifying the DAC converter. We do this by first copying the "sim_Ideal_ADC_DAC" and renaming it to"sim_My_ADC_DAC" . We also copy the components, "Ideal_DACbit", "Ideal_10-bit_DAC" and rename them accordingly. We should get 3 new files that we can modify without changing the original design.

• In the actual design, we start by deleting the Ideal_10-bit_DAC (component on the right), and replacing it with our own My_10-bit_DAC.
  

• We then descend edit our custom My_10-bit ADC by selecting the component and pressing shift+x
• We then delete each of these Ideal_DACbit with our own custom My_DACbit.

• We then descend edit our custom My_DACbit by selecting the component and pressing shift+x
• We then modify this circuit by following the schematic in Fig. 30.14 from the book. Here we implement a 2R resistor with two separate 10k resistors in series.

• Remember that for each cell the we modify the pins, we have to re-create the symbol, otherwise we would get an error when we do the save and check. We can do this by creating a new cell.

• We then select the From View Name as symbol and hit OK.

• Remember that the symbol is rectangular in shape, we have to designate where we want our pins to show. Wheter it would be on top, bottom, left or right. After we change these settings hit OK.

• Hit save and check to save our new custom symbol.

• We update the symbols for the other two cells that we modified.
  
• We go back to out top diagram, sim_My_ADC_DAC. After you've designed and drafted your schematic check and save it. Hopefully we get no errors.

1. In order to dertermine the output resistance of the DAC, we remove all our voltage sources, this means connecting all our inputs, B0-B9 to gnd, then combine all the parallel and series resistance. If we do the hand calculations, we can notice that as more bits are getting added to the circuit. The total output resistance will get closer to R. For an 10-bit DAC converter, we get the R to be around 9999.986 Ohms.

1. Ground all DAC inputs except B9. Connect B9 to a pulse source (0 to VDD) and show, and predict using 0.7RC, the delay the DAC has driving a 10 pF load. We can calculate the delay of DAC is 0.7RC=0.7(10k)(10p)=0.07us=70ns. The simulation result in following image proves the calculation.
• Here is the circuit indicated above.

• Here is the results of the simulation. Notice that the voltage in the capacitor output goes only up to 2.5V due to the output resistance of the circuit. Half of this, 1.25V is the 0.7RC mark which we get 71.36ns, which is close to out hand calculated values.
  

1. How to create a symbol view for your design with the exact same footprint as the Ideal_10-bit_DAC symbol view  (hint: use Copy before you start drafting your design, e.g. Copy the cell Ideal_10-bit_DAC to Mydesign_10-bit_DAC and then simply edit the schematic view!)
This was mentioned before in item number 1. step ... click here

2. Simulations to verify your design functions correctly. Using our modified circuit shown below. We can run several simulations involving different RC combinations.

• In this simulation, we drive a resistive load.

• In this simulation, we drive a capacitive load.

• In this simulation, we drive both a resistive and capacitive load.

• In this simulation, we drive both a resistive and capacitive load.  If the load is only one resistor, 10k, only the amplitude will be half of the input signal.  Because output resistance is R, 10k.  

                               

1. In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). In the real circuit, the switches will use transistors. Due to the transistor has parasitic resistance,  therefore, each 2R should plus the parasitic resistance. The problem is that when the parasitic resistance is larger than 2R, the output voltage will go down. This is because there would be significant voltage drops across the parasitic resistance.

1. Lastly, we back everything up through dropbox.

Finally, backup your design lab2 directory and other files for future study.