Lab 8 - ECE 421L 

Authored by Silvestre Solano, Nha Tran, John Huang

Email: Solanos3@unlv.nevada.edu

trann4@unlv.nevada.edu

huangj19@unlv.nevada.edu

 

The purpose of this lab is to implement at least the following test structures on a standard 40 pad chip frame. The first task for chip testing is a visual inspection to see if there are any obvious imperfections. To test the chip, the chip must be hooked up to  proto board which will then be connnected to an oscilloscope probe. To test any of the resistors, the resistors will have its resistance measured with a multimeter. To test the 61 stage oscillator, a square wave will be input to the oscillator and the output will be observed. To test the VDD, an input voltage will be input and it will be gradually increased from 0 to 5 volts and the current will be measured. If the current exceed the expected value, then a short circuit may be present. 

  

  

The chip frame diagram is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/dip40.jpg

The test structures with their corresponding pin numbers are shown in the table below.

 

1)DN11) VDD_osc21)31)
2)GN12) OCS_Out22)32)
3)SN13) 20K nwell23)33)
4) DP14) 20K hires24)34)
5) GP15) 1K N+25)35)
6) SP16) 1K P+26)36)
7) BP17) P+ VDD27)37)
8) out18) VDD_bg28)38)
9) in19) Vref29)39)
10) VDD_inv20) gnd!30)40)

The completed chip schematic is shown below. The p+ and n+ resistors are not shown in the schematic because the layout would not LVS properly. The p+ and n+ resistors are covered with the nodrc layer.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/13.JPG

 

The layout is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/14.JPG

 

The successful DRC of the layout is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/15.JPG

 

The succesfull LVS is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/16.JPG

 

The layout of the poly2 resistor is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/1.JPG

 

The layout of the nwell resistor is shown below.

  

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/3.JPG

The layout of the n+ resistor is shown below

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/11.JPG

 

The layout of the p+ resistor is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab8/12.JPG


 

The design directory is found in this zip file.