Lab 7 - ECE 421L 

Authored by John Huang.

Huangj19@unlv.nevada.edu

October 27, 2014

In this lab we will see implementions of NAND, NOR, AND, OR, MUX and inverter gates using 6u/0.6u MOSFETS.

We will create schematic views and symbol views of these when they are single bits and 8 bits.

We will also create a schematic of another full adder and lay out the full adder.

First let's look at the inverter.

We will edit its properties changing the instance name to I0<3:0> which gives it an array.
In this case it is a 4 bit array from 3 to 0.

We will also use wide wires meant for buses to implement the array.
We create pins that correspond to the array number.

Using this schematic we can now create a symbol for a 4 bit inverter.

I labeled this X4 (4 bits) to differentiate this from a 1 bit inverter.

We can now simulate this 4 bit inverter with the following schematic.

We can run a transient analyses to see how this inverter array works.

As you can see each output has its own graph because of the way the array is set up.

The capacitive load delays the output of the pulse. The higher the capacitance value the bigger the delay.

We can also see that the rise and fall times takes much longer when you have a higher load.

Let's now create a 8 bit inverter.

Change the array to <7:0> giving it 8 bits.

The schematic of the 8 bit inverter.

We can create a 8 bit inverter symbol from the schematic.

We will look at the process of all the gates at once after we create all our gates.

 
Now the 8 bit NAND gate.

The symbol view of the 8 bit NAND gate.

Now let's create a AND gate.

To do this we can simply add an inverter to our NAND schematic.

Then create a symbol from the AND gate.

Now take the symbol and make it an 8 bit AND gate array.

Then create the symbol for the 8 bit AND array.

Now we can create a schemtic of the NOR gate.

The symbol for the NOR gate.

Schematic for the 8 bit NOR array.

The symbol for the 8 bit NOR array.

The schematic for the OR gate, just add an inverter like for the AND gate.

The symbol for the NOR gate.

The schematic for the 8 bit NOR gate.

The symbol for the 8 bit NOR gate.

We can now simulate these gate arrays.

Now we can create a MUX.

The schematic of the MUX.

Creating a symbol for the MUX.

We can simulate our MUX symbol to see how it operates.

We can see in the graph that if depending on Si, the MUX will choose the value of A or B.

We can also create a DEMUX by adding an inverter for the S input feeding into the Si input.

Now we can create the DEMUX symbol from the schematic.

With the DEMUX symbol we can now make a 8 bit DEMUX symbol.

First the schematic of the 8 bit DEMUX.

Then the symbol for the 8 bit DEMUX.

We can simulate our 8 bit DEMUX symbol to see how it operates.

We are now going to recreate the full adder seen on Fig 12.20 from the CMOS book.

The schematic of the adder.

The symbol view of the adder.

The 8 bit adder schematic.

The 8 bit adder symbol.

The layout of a single adder.

The 8 bit adder layout.

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