Lab 6 - ECE 421L 

Authored by Eduardo Hoyuela-Alcaraz,

October 20, 2014 

Email: hoyuelaa@unlv.nevada.edu

   

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder.


LAB WORK

In this lab we will use the inverter used in lab 5.

Using Tutorial 4 we drafted the schematic, layout, and symbol of a NAND gate having the following characteristics:

1. 6u/0.6u PMOS and 6u/0.6u NMOS. 

Schematic and symbol

FIG_1FIG_2

Then we created the layout with input and outputs on metal 1 and perform a DRC and LVS check.

Layout
FIG_3		Extracted
FIG_4
DRC check
FIG_5		LVS check
FIG_6

Then we will create the schematic, symbol and layout of an XOR gate using 6u/0.6u MOSFETS

FIG_7FIG_8

This layout is more complicated. We will need to use metal 2 layer to create some connections. All inputs and outputs will be on metal 1.

Layout
FIG_9		Extracted
FIG_11
DRC check
FIG_10		LVS check
FIG_12

Before going any further we proceed to check the outputs of our NAND and XOR gates. 

We create a schematic and then run a simulation.

FIG_13
FIG_14
It is seen that there is a glitch in the XOR gate, this happens because of the rise time and fall time for each gate. We are concerned about this glitches if our application requires a fast response that is in the nano second range or even smaller.

Our next step now that we have verified the operation of our gates, is to create a full adder.

First we create the schematic and then the symbol.

FIG_15FIG_16

Now we proceed to create the layout and perform the DRC and LVS checks.
Layout
FIG_19
DRC check
FIG_21
Extracted
FIG_20
LVS check
FIG_22

Finally, we simulate the full adder to verify its operation.
FIG_17
FIG_18
It is observed that there are glitches again, but this is fine as our design does not require speed and will not operate at high frequencies.

 

This lab is done and now we back up our files in Google Drive and on our desktop.
 
FIG_23FIG_24



Download LAB_6_ HOYUELA_EDUARDO


Return to EE 421 Labs