Lab 5 - ECE 421L 

Authored by Eduardo Hoyuela-Alcaraz,

October 13, 2014 

Email: hoyuelaa@unlv.nevada.edu

Design, layout, and simulation of a CMOS inverter.

LAB WORK

Using Tutorial 3 we drafted the schematics, layouts, and symbols of two inverters having the following characteristics:

1. 12u/6u PMOS and 6u/6u NMOS. We will call it “INVERTER_1”.

2. 48u/6u PMOS and 24u/6u NMOS. We will call it “INVERTER_4”.

We created the PMOS and NMOS devices for point 2by setting the multiplier equal to 4.

Schematics

After creating the schematics, we proceeded to create the Symbols

Then we created the layout both inverters and we DRC them to see we are not violating any design rule

Then we need to extract the view and do an LVS to verify that our layout matches the schematic.

 
Now that we have created both inverters, we need to test them and compare how they work when we apply a load of 100fF, 1pF, 10pF, and 100pF.

We will use two simulators, Spectre and Ultra Sim.

We will create the following schematic to simulate them.

Now we proceed by selecting the appropriate capacitor value and simulate our inverters.

It is observed that Inverter_4 has a smaller rise and fall time when we compare it to Inverter_1. This happens because the Inverter_4 allows more current to flow through it because the path is wider between the drain and the source.

UltraSim is less accurate than Spectre but it is faster for analyzing big circuits. On this lab no difference was noticed between using Spectre and UltraSim

Download LAB_5_ HOYUELA_EDUARDO

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