Lab 3 - ECE 421L
LAB WORK
We will use the n-well to create a 10 k resistor to use it for the layout of the DAC schematic.
This n-well 10k resistor was completed previously as part of a homework
assigned in the lecture.
For the C5 process the CMOS design rules have a lambda of 300nm and a
technology code of SCMOS_SUBM. The sheet resistance for the C5 process is
approximately 800Ω.
The rules specify the following:
1. Minimum width of 12λ
2. Minimum spacing of wells at different potential of 6 λ
3. Minimum spacing of wells at different potential of 18 λ
Knowing these we proceed to select the n-well layer on the Layer Selector
Window (LSW).
The rectangle we will need to layout will be defined from the following
formula
R= Rsheet * (L/W).
The L/W ratio is then 10k/800 which is approximately 12.5.
We then know the minimum width is 3.6u so then we select the width to be
W=4.5u. This leaves the Length to be L=(12.5*4.5)=56.25u.
We know that the DRC will give an error as in tutorial one if the
dimensions are not divisible by .15u because they will not snap to the grid.
We checked that length and wide were divisible and we got W/.15= 30
and L/.15= 375.
After laying out the box we add the ntaps on each side, we connect pins (left and right) drawn in the metal1 layer and add the res_id layer. We DRC to check everything is correct..
Then we extract the view and we see that the total resistance is 10.1kΩ.
Then in the R2-R cellview we create a layout. In the layout we will instantiate 3 n-well 10k resistors. We will stack them and connect them by using metal1.
The minimum spacing between these
resistors should be 18λ or 5.4u.
The pins that need to be added are left (input), top(in/out), and bot(in/out) so that it matches our R2-R schematic.
Then we proceed to DRC to check that everything is correct.
Then we extract a view from our R2R layout.
Finally, we LVS the extracted view with the schematic and we see that everything matches.
We have now created a layout for the DAC.
Download LAB_3_ HOYUELA_EDUARDO