Lab 2 - ECE 421L
PRELAB WORK
Dowload the simulation
example and upload to your directory.
It is very important to define the new statement in the cds.lib for the simulation example to show after starting Cadence.
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Open the schematic view of sim_Ideal_ADC_DAC
Launch ADE L and run the simulation. The loaded state is a transient analysis with duration of 1000ns with Vin and Vout as outputs for the plot.
We will modify the DAC by creating our own 1-bit DAC using 10 k resistors. We will name this design R2R.
Then we will create a symbol from our schematic we will use it in the DAC schematic.
Then we open the copied 10bit DAC schematic and replace the components with our R2R symbol and we update the symbol too.
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Then we check that the top schematic updated after doing the changes in the DAC
Then we check the output by running again the prelab simulation.
We see that the output is the same as the one in our prelab. Therefore all changes made we implemented correctly.
We now proceed to calculate the output resistance in the DAC.
 | Our DAC has the same configuration going from b0 to b9. To calculate the output resistance we ground b0 through b9. Starting from b0 we observe we have 2R in parallel with 2R, the equivalent resistance is R which is then in series with R and parallel with 2R of b1. This pattern repeats all the way up to b9. Therefore the output resistance is R. In our case R=10kΩ |
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The driving load delay is calculated by 0.7RC T= 0.7(10k)(10p)= 70 ns. We know that the output will be half of the input because
our DAC acts as a voltage divider in this configuration. |
 | As seen the output voltage is approximately 2.5V and the rise time is about 75ns where the output is half of its expected value. |
Then we proceed to analyze the effects of adding a 10K resistor to the ADC-DAC circuit.
We expect to se the output drop by half of its original output because the output resistance of the DAC is 10k. The 10k resistor in parallel with the output resistance acts as a voltage divider.
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Then we replace the 10K resistor with a 10pF capacitor. It is expected that the capacitor will delay the output signal.
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Also, the capacitor made the output signal smoother.
Then we analyze when the DAC is driving a RC load.
 |  It is seen that the output is shifted and it is half of the input. The output is also smooth. |
If we used switches, we would need to make sure that their resistance is negligible. If they have a high resistance the effect seen would be of a smaller magnitude output as the output resistance would be higher.
The LSB is the voltage step required to represent a new value. It is calculated by this formula LSB= VDD/2^n, where we use 2^n as a binary combination of high or low, where n represents the number of inputs. For our DAC we have 10 inputs that result in 1024 possible combinations, so our LSB is LSB=(5V)/1024= 4.88mV. For example if our input is 1111111111 (1023) our voltage output would be Vout= 1023*LSB= 4.99V. Again, if input is 11110000 (240), the output is Vout= 240*LSB= 1.17V.
The lab is done and now we backup our files.
Download LAB_2_ HOYUELA_EDUARDO