EE
421L Lab 3
Authored
By Alan Fortes
on September 28, 2013
fortesa@unlv.nevada.edu
The
follwing lab will finish up tutorial one and layout the DAC from lab 2
using n-wells. Here is the zip files containing the lab directory:
Lab3.zip
Part 1: Finishing tutorial one
Here is our original circuit where we left off from, in Lab 1.
Our circuit is strippied of the voltage source and all adjoining wires.
We add a pin to the end of the wire between the resistor and the voltage source.
Below, the pin creation option is selected.
This opens the add pin menu, which we can name our pin an appropriate name.
We do the same for the out pin.
Here is the finish circuit.
The circuit is then checked and saved to ensure it is functional.
After checking and saving, the circuit is going to be made into a symbol for the convenience of having it as an instance.
Below, the first step starts by selecting create, cellview, and from cellview.
After clicking cell view, this menu is brought up.
Clicking OK will bring up this menu which will allow us to make sure the specifications of the symbol are correct.
After
clicking OK, we get this symbol below. The generic rectangle in the
middle will be deleted and replaced with a meaningful symbol.
After
the deletion, these are the only 2 parts that must remain. Using the
line tool, as seen below creaete symbol seen below the photos seen
below.
Here is the symbol that must be created.
After creating that symbo, copy the R_div cell by do as seen below.
After
clicking copy, the menu below apears. Make sure the fields below are
filled with the appropriate information, as seen below. Be sure to
delete spectre_saved1 in the R_div cell, and delete the symbol
view in the sim_R_div cell.
Open
the schematic view of the sim_R_div cell and delete the contents of
that cell. Insert an instance of the symbol we created earlier, as seen
below.
Set up the circuit, as seen below. The L button will allow you to set up appropriate labels.
Be sure to give the voltage source 1 volt, as seen below.
After having set up the circuit properly, check and save it.
You may get warnings. To ignore those, simply click check, find markers, then ignore, and apply.
After having taken care of that, click Launch, ade, session, load state, cell view, and OK, as seen below.
After loading the state, select the outputs label at the top of the ADE, to be plotted, and select on schematic.
Click on the In and Out labels on the schematic.
After
clicking on the labels on schematic, click the run button, the green
one with the triangle, and expect to the see the output below. The
colors will
be different, but you should get an In of 1 volt and an output of 0.5.
After running that simulation, create a new library. Title this libray R_n_well_10k.
Create a new layout cellview of this library.
Select the nwell from the layer options seen to the left, and select create, shapes, and rectangle, or press the R Key.
Lay down a rectangle of any shape.
Click the rectangle, and press the Q key. Make the rectangle's left, right, bottom, and top dimensions as seen below.
Push the I key and get the ntap cell. Make sure the cell is lower case, and the number of columns is 2.
Place one square at the ends of the nwell as seen below.
To see the actual nwell's, press the E key, and change the zero in the stop box, to a 10.
Now, the ntaps can be seen.
Now, click the metal1 selection, as seen to the bottom left, and then click create, and pin.
Make
the name of the terminal L, and click the display terminal name
checkbox. Click at the bottom left of the blue rectangle of the ntap,
and then click at the top right.
Do the same thing for the right ntap.
The end result is seen below.
Click
the res_id selection as seen below, and then click the bottom left of
the large nwell rectangle, not including the ntaps, and then click the
top right.
The end result is seen below.
Click verify and extract.
Navigating to the extracted file, we can see the resistance of the block, is roughtly 10k ohms.
Now, we can use this resistor to create a 1 to 2 voltage divider.
Open the layout view of R_div. If you haven't created that cellview, create it.
As
seen below, create the following layout, by putting in intances of the
10k resistor we made, and putting metal1 and pins over the ntap
contacts.
Save the layout you created, and extract it.
Run an LVS of the extraction with the schematic of the divider created earlier.
This verification show that the diver works, and matches the schematic.
Part 2: Using our layout tools to create a DAC.
According
to the MOSIS submicron design rules, the minimum width of the nwell
block must be 12 lambda, or 12 times .3micrometers. This means that the
minimum is 3.6 micrometers. To accommodate the spacing of our ntap, the
width of our block will be 4.5 microns, satisfying
the MOSIS rules. To find the length we simply use algebra:
10000 = 800*(L/4.5), L = 56.25.
Our length will be about 56 microns.
The length and width are ensured by using the ruler tool, easily accessible by pressing the K key.
Here is an individual DAC unit, which will comprise the whole DAC unit.
The individual DAC unit after a DRC confirmation, indicating success, with zero errors.
Here is the extracted view of the indvidual DAC unit layout.
The individual DAC unit matches up with the schematic DAC unit.
This the DAC, composed of 10 DAC units stacked on top of eachother, and connected with metal1 streams.
The DRC shows success.
Here is the extracted view of the DAC's layout
The DAC of lab2 matches up with the layout.
Here is an upclose screenshot of the layout showing the corresponding binary input pins.
