EE 421L Lab 2
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6th: After having run the simulation, you should get a graph similar to the one below. To change the background from black to anyother color, right click on the graph and click graph properties, you could press the shift and q keys at the same time. Click the black square and select your desired colors. To change the color and style of the graph traces, right click on the traces, or trace names, and select color, style, or one of the other properties. | |||||||||||
Varying output of the original circuit:
If the input of the circuit is changed to exceed what the circuit is meant to handle, the output will not go above that input.
The same goes for negative voltage. Our converter can not handle negative voltages and will flat line when reaching the bottom.
Our converter is made to handle a maximum of 5 volts.
Any input that falls between 5 and 0 volts will be quantized and output.
The general circuit schematic:
In order to create a digital to analog(DAC) conversion unit, we will use a set of resistors in the order seen below. We will use 10kilo Ohm resistors for every instance of R, meaning that the resistor 2R will be composed of 2 10kilo Ohm resistors. Each of the 2R and R units will be made into a symbol and the symnbol will be placed inside of the main DAC unit. Here is the schematic of the 2R and Rs.
The creation of resistor based DAC unit:
Each of the 2R and R units will be made into a symbol and the symbol will be placed inside of the main DAC unit.
Here is the schematic of the individual 2R and R. The in pin takes in voltage of the digital binary signals. The top
of the unit of the most significant bit will be the quantized analog curve. The top of the other units will connect to
the bottom of the other units. The bottom of the last unit will be connected to a 20k resistor, and ground.
This schematic will placed inside of a symbol and the symbol will will be placed in series, as seen in figure 30.14.
Here are the 10 2R and R units strung together in series. This schematic below is copied into a copy of the 10_bit_Ideal_DAC. This new copy is called my_10_bit_Ideal_DAC.The total resistance of the 2R and R units come out to be simply R. This can be easily should be calculating the total resistance through the circuit.
At the bottom of the circuit, the resistance of 2R and 2R in parallel become R, (2R * 2R)/(2R + 2R) = R. This R is added to the resistor above.
This makes a 2R, which is in parallel with the 2R to the left of it. This process repeats untill we are left with a lone pair of 2Rs, which is finally just R.
Part 3, Testing the Design: Getting meaningful output.
Here is a schematic of my circuit using the resistor based DAC.
The output of my circuit show a nearly identical output as the original circuit. The exception is the small pit at the beginning. Other than that, the output is
identical to the original circuit.
Now,
we will place a 5 volt pulse to the B9 input port, ground the rest, and connect the output to a 10pico farad capacitor.
By activating the B9 port, we will get a binary value of 512, out of
our 2^10, or 1024, bit DAC. This means that have
of the voltage will be output, 5 * 512/1024 =2.5. I predict that the delay of the halfway point will be 0.7 * 10picoFarads * 10,000Ohms, which will ultimately be 70nanoSeconds.
Here
is the set up:
Here is the my circuit driving a 10k resistor.
Here is the output from the DAC driving a load of 10k. The output can clearly be seen to be around the 2.5 volt mark. This is happening because the 10k resistive load is in series with the 10k resistance total of the DAC circuit. This creates a voltage divider with a ratio of 1/2,
output to input.
Here
is my circuit drving a load of 10pico Farads.
The output has become smoother, but slightly reduced. The reduction occurs due to the impedence of the capacitor.
The smoothness occurs to the accumulation of voltage rising in the capacitor.
This circuit combines the smoothness of the capacitor, with the voltage reduction of the resistor.
Part 4, Digging a little deeper:
In a real circuit the switches seen above (the outputs of the ADC) are
implemented with transistors (MOSFETs).
If the resistances of the switches are not small compared to R, then the switches would rob the the DAC unit of the adequate voltage necessary to output a decently quantized value, reducing the actual output to 1 minus the ratio of the switch resistances to DAC resistances percent. For example, if the switches' resistances where .01 of R, the output voltage would be 1 - (0.01R/R) = 0.99, or 99 percent of the original input. This change is negligible. But, if the switches were 0.5 of R, then the output voltage would be 1- (0.5R/R) = 0.5, or 50 percent of the orignal value. This is a drastic change from the accuracy of what we'd expect.
Part 5, Backing up the lab:
To
ensure that this lab is not lost to eternity, both the lab folder
containing my lab report, and the data of the circuit are zipped up
and emailed to myself.