EE 421L Digital Integrated Circuit Design -
Lab 4
Author: Abel De La Torre
Octover 6th, 2014
delatorr@unlv.nevada.edu
IV characteristics and layout of NMOS and PMOS
devices in ON's C5 process
===============================================================================================
Pre-lab work
- Back-up all of
your work from the lab and the course.
- Read through this lab before starting it.
- Go through Tutorial 2
- In
the simulations in this lab the body of all NMOS devices (the
substrate) should
- be at ground (gnd!) and the body of all PMOS devices (the
n-well) should be at a vdd! of 5V.
Next add Pins with the direction inputOutput
and wires as seen below.
Remember that right+clicking the
mouse when instantiating the Pin rotates it.
Z (zoom out by 2) and f (fit) can be used while instantiating
the pin.
w can be used to wire the
Pin to the MOSFET.
Check and Save the schematic when finished.
Next, Draw a MOSFET symbol and move the pins (rotate as necessary)
to get (something similar to) the following. Remember to draw a line use Create -> Shape -> Line.
Adding the width and length text using Create -> Note
-> Text
When finished “Check and Save”
Instantiate the NMOS_IV_Cell
View
just created and the DC voltage sources seen below (and wire things
together). Go to File -> New -> Cellview, you must selct
schematic option at the top.
Now
we must select the correct model library in the ADE. Select ADE
from the Launch tab then select setup and find the model libraires as
shown below.
Next, do the DC analysis as shown below.
Next,
select the variable for VGS, select variables -> edit -> and
enter value. now, select tools and parametric analysis and enter
the setting as shown below.
The following is the simulation after the execution.
The following displays the the body and the gate of the NMOS along with its pins
After the layout is DRC the NMOS is then extarcted as shown below.
Next we follow the same steps for a PMOS. A
schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device
for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies
from 0 to 5 V in 1 mV steps. Use a
12u/600n width-to-length ratio. The following is the simboy of a PMOS
Next add Pins with the direction inputOutput
and wires as seen below.
Remember that right+clicking the
mouse when instantiating the Pin rotates it.
Z (zoom out by 2) and f (fit) can be used while instantiating
the pin.
w can be used to wire the
Pin to the MOSFET.
Check and Save the schematic when finished.
Instantiate the PMOS_IV_Cell
View
just created and the DC voltage sources seen below (and wire things
together). Go to File -> New -> Cellview, you must selct
schematic option at the top.
Now
we must select the correct model library in the ADE. Select ADE from
the Launch tab then select setup and find the model libraires as shown
below.
Next, do the DC analysis as shown below.
Next,
select the variable for VGS, select variables -> edit -> and
enter value. now, select tools and parametric analysis and enter the
setting as shown below.
The following is the simulation after the execution.
=================================================================
LAb requirements Schematic for simulating ID v. VDS of an NMOS device for
VGS varying from
0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV
steps. Use a 6u/600n width-to-length ratio.
The following is the resulting simulation of the schematic
A
schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV
where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.
The following is the resulting simulation of the schematic
A
schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device
for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies
from 0 to 5 V in 1 mV steps. Use a
12u/600n width-to-length ratio.
The following is the resulting simulation of the schematic
A
schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV
where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.
The following is the resulting simulation of the schematic
=============================================================================================
NMOS Layout with probe pads attached to the 4 terminals
This is the schematic of the NMOS
The NMOS LVS check of the schematic and extarcted view
This is the schematic of the PMOS
The PMOS showing DRC with no errors.
The following is the stracted view of the PMOS.
The following is the schematic that gets LVS to verify a match
Last part, Back up files.
creat a zip/rar file for lab4
Next Email it to yourself
