Lab 6 - EE 421L
2. go through tutorial 4 where you create a nan layout and schematic.
nand schematic:
nand symbol:
nand layout :
nand LVS:
Next we need to create a simulation testing the nand gate.
This was my output : make sure you dont forget to add in your model libraries for the simulation. I did a transient analysis for 25ns.
Lab: now we have to do the XOR and ALU.
XOR schematic:The schematic we found in the book and put it in cadence with pmos and nmos. Like the nand but more complicated.
This was my smybol for the schematic:
My layout: this layout is much more complicated than the nand layout so be careful about connecting metals across metals. I used metal 2 connections so that I could cross over poly and metal 1 without shorts unless i used a via or m1_poly connection. This is my layout plus LVS. The metal 1 connection to the very right of the A block is my Ai pin. But on my schematic i used no connection so that I didnt have to make a pin for it. if you want to make a pin for it then you have to change your schematic accordingly.
Now we had to simulate the XOR to test if it worked properly: This is my schematic.
This was my output at trasnsient analysis for 25ns:
Next we move on the the full Adder.
This was my schematic using the nand and xor symbols we made :
This is the layout: This was the most time consuming part of the lab. You have to make sure that the connectiuons do not short on any others so using metal 2 connections were very useful. Also I found that if you line up the pmos and nmos to perfectly match up it makes the connections easier and cleaner. It helps to have the schematic on the side when you are drawing the connections and to drc it as you go so you dont have a lot of errors in the end just incase. Also remeber to delete the nmos connections in the middle so you dont short the metal 1 connection. for example where Cout is.
This is the LVS of the layout and schematic.
Next we had to simulate the Full adder to make sure it worked properly. this is my schematic:
This was my output graph.
This is me backing up lab 6:
