Lab 7 - ECE 421L 

Elizabeth Baldivias

baldivi3@unlv.nevada.edu

Using buses and arrays in the design of word inverters, muxes, and high speed adders.

Create a schematic for inverting a 4 bit word

By instatiating the invertere and naming it as an array, the same came be accomplished.

A symbol needs to made for this array of inverters.

A schematic was created in order to simulate.

 
The following output was given,

As seen through the output, the greater ther capacitative load, the greater the delay of the output.

Next part of the labe was to create schematics for 8 bit input/ output arrarys of NAND, AND, NOR, and OR gates.

It was also required to simulate these gates to show their operation.

NAND 

The schematic of the NAND was used from the NAND from the previous lab.

A symbol was created from the schematic.

 
Using this symbol an 8 bit array was created with the following schematic.

 
A symbol was created for the 8 bit NAND.

 
Once the symbol was made a schematic to simulate the operation of the gate was made.

 
The NAND gate gave the following output.


 
AND
 
The schematic for the AND gate was made using the NAND gate and adding an inverter to the output.

 
A symbol was created from the schematic.

 
With this symbol an 8 bit AND gate schematic was made.

 
From this schematic a symbol was made.

 
Once the symbol was made a schematic was made to simulate the operation of the gate.

 
The simulation gave the following output.

 
NOR
 
This was the shcmeatic used for the NOR gate.

 
A symbol was created from the schematic.

 
With this symbol the 8 bit NOR gate was created.

 
A symbol was made for the 8 bit NOR gate.

 
A schematic using this symbol was made to simulate the the operation of the 8 bit NOR gate.

 
Simulating this schematic gave the following output.

 
OR

The schematic for the OR gate was mad by adding an inverter at the output of the NOR schematic.

 
An OR symbol was created from this schematic.

 
With this OR symbol the 8 bit OR schematic was made.

 
From this schematic, the 8 bit OR symbol was made.


 
Once the symbol was created a schematic was made to simulate the 8 bit OR gate.

 
The following output was given.

 
 
The next part of the lab was to examine the 2 to 1 MUX/DEMUX.

Here is the schematic for a MUX, and the symbol created for it.
 
 
Since S and Si are used, Si can be taken out by adding an inverter to S. 

 
This was the symbol created from not using an inverter.

 
MUX works in that when S is high, the output of Z is A. When S is low, the output of Z is B. A DEMUX works in the same wasy that  MUX works, but instead A and B are outputs and Z is the input. There will only be 1 input and it will have various possible outputs (ex. A or B).
 
 
Once the symbol for the MUX was created, a schematic for the 8 bit MUX was made.

 
A symbol for the 8 bit MUX was made from the schematic.

 
Once the symbol was created a circuit was made to test the output of the gate.

 
This circuit gave the following output.

 

The next part of the lab was to create the Full Adder in Fig.12.20.

 
This is just 1 bit. A symbol was made for the full adder.

 
With this symbol an 8 bit full adder schematic was made.

 
Using this schematic a symbol was made.

 
The next step was to simulate the operation of a full adder, this is shown below.

This was the output given.

A layout was needed to be made of the full adder. The way I created the layout was by making a layout of the 1 bit full adder.

I LVS'd against the 1 bit schematic until the netlists matched.

 

 
 
Once the 1 bit layout LVS'd I used this layout and copied it 8 times to create the layout for the 8 bit full adder. I made sure to connect the output to the input of the next layout by using  metal 2 to cross through the 8 different parts of the layout. I renamed the pins to A<0>, B<0>, and s<0> ....so on until we reached 7. Also cin was only at the first part of the layout and cout was only to the last part of the layout. This was the resulting layout.

 
The netlists matched.


 
Here are snips of the first full adder in the layout and last full adder of the layout.



This is the end of the lab.

I zipped up my cadence directory and it can be found here.

I also made back ups of my directories and uploaded them to a google drive folder.
   
 

Return to EE421 labs here.