Lab 6 - ECE 421L 

Elizabeth Baldivias

baldivi3@unlv.nevada.edu

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder.

Pre-Lab

    - Read through the lab in its entirety before starting to work on it

Pre-Lab Work
 
First part of Tutorial 4 helps you create a schematic of a NAND gate. Here is the schematic created and check and saved.
 

 
The next step was to create a symbol of the NAND gate similar to the actual symbol used to represent a NAND gate.


 
Once the symbol was created the shematic for the simulation of the gate was made. A 100f capacitor load was used along witht they symbol, vdd, and a vpulse with paramters of Voltage 1 = 0V, Voltage2 = 5V, Delay Time = 10 ns, Rise Time and Fall Time = 1 ns, Pulse Width = 20 ns, Period = 40 ns.

 
Launchind the ADE-L and setting up the parameters produced the following:

 
This was the resulting output.

 
The next part of the tutorial was to create a layout of the NAND gate. By overlapping two PMOS and overlapping two NMOS MOSFETS, adding pins, connecting with metal 1, and flattening and deleting the metal1 contacts between the NMOS, and connecting to vdd! and gnd!, produced the following layout and extracted view.
 
 
After verifying that it passes DRC and verifying LVS, the schematic and layout match.
 
 
This concuded Tutorial 4.

Lab Work
 
Draft the schematics of:
    - 2 input NAND gate
    - 2 input XOR gate
    - Create layouts and symbol views showing that the cells DRC and LVS without errors
    - Using spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, 11)
   
Creating the 2 input NAND
 
Creating the 2 input NAND gate didnt require much work since it was created in the pre-lab work. All I did was edit the symbol to add the gate name and my initials.
 
Schematic

 
Symbol

 
Layout and extracted
       
 
After verifying DRC and verifying LVS the layout and schematic match.


 
Simulating the operation of the NAND gate was done by creating the following schematic. The following parts were used: the NAND symbol, VDD to apply voltage, 2 vpulse to create the A and B inputs, and a no-connection for the output. To create the A input voltage 1 was set to 0V, voltage 2 was set to 5V, and the period was set to 10 ns. To crete the B input i set the parameters the same to the A vpulse but set this vpulse to a period of 5 ns.

 
The ADE-L was set to a transient analysis of 30 ns.

 
This was the resulting output.
 
Imperfections on the output of the gate are caused by timing delays of the inputs.
 
Creating the 2 input XOR gate.
 
The 2 input XOR gate was made by drafting the following schematic.

 
A symbol was created from the schematic to resemble an XOR gate.

 
A layout of the gate was made. The key to making this layout was to use metal2 to be able to cross over metals.

 
Extracted version.

 
After verifying DRC and verifying LVS, the schematic and layout match.


 
To simulate the operation of the XOR gate a copy of the schematic of the simulation of the NAND gate was used. All that was changed was the symbol. The NAND symbol was removed and the XOR symbol was used, the wire named "AnandB" was changed to "AxorB" to create the following schematic.

 
The ADE-L was set to the following parameters.

 
This was the given output.
 
 

Using these gates, draft the schematic of a full adder.
    - Create a symbol of the full adder
    - Simulate the operation of the full adder symbol using the symbol created
    - Layout the full adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
 
The following schematic was created by using the NAND and XOR gates.

 
A symbol for the full adder was created from this schematic.

 
The next was to create the layout version of the full adder. This layout was made by making copies of the NAND layout and the XOR layout. ntap columns were increased for vdd! and ptap columns were increased for gnd!. Again, metal2 was used to be able to connect and crossover other metals. m2_m1 and m1_poly connects were used in overlap whenever a poly connection was needed to be made. m2_m1 was used when making connections to metal2. a, b, cin, cout, and s pins were created to match the schematic.

 
Extracted

 
After verifying DRC and verifying LVS, the netlists matched.


 
Next step was to simulate the operation of the full adder. A shcmatic using the full adder symbol was used. Vpulse was connected to a, b, and cin. a was set to voltage1 = 0V and voltage2 = 5V, with a period of  5 ns.

ADE-L was set to the following parameters.

 
The following output was given.

 
The next part of the lab was the simulation of the following schematic.

 
The following ADE-L was used.

 
The following output was given.

I zipped up my folders and uploaded them to google drive to back up all my work.

Click here for  lab6_EB.zip

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