Lab 6 - EE 421L

Authored by: Medhanie Petros

E-mail: petrosm@unlv.nevada.edu

Date: 10/14/2013

Lab description

1.  Go through the tutorial_4 and Electric_video_11, learn to design the schematic and layout of nand and nor gates.

2. Follow the lab6 descriptions to design nand, nor, xor gates. Use LTspice and IRSIM to simulate these gates.

3. Use designed gates to make two types of full adder. One consists of two xors and two nands, one nor and three inverters. The other one is implemented by 3 nand and 2 xor gates.

2. Backup the Lab report and upload it to the CMOSedu.com for the future study and discussion.

Discussions & Captured Images:

NAND gate design:

By following the steps talked in tutorial_4. I design a NAND gate using 10/2 MOSEFTs.  

From the tutorial_3.jelb designed before and duplicate the inv_20_10 cell.

Then delete all the wrie Arcs, icon view and remain the PMOS/NMOS and vdd, gnd.

Change the MOSFETs size into W=10, L=2. Rename the cell as NAND_wwl_f13.  

Copy and paste to put two 10/2 PMOSs and two 10/2 NMOSs in the NAND cell.  

Connect these MOSEFETs and export the off-page nodes as the following NAND circuit. 

Using the artwork make an icon view.  

The circle, pin and polygon are used in to design the icon and the command "Toggle Outline Edit"

is also useful to change polygon. About the circle, change the degrees to 180 in the node properties. 

Checking the design, let's simulate the NAND gate. 

Connect one input to VDD and give a pusle signal to other input node. 

wave form of the NAND 

Move to lay out the NAND cell. 

The inv_20_10 contains the MOSFET layout. Only change the PMOS size and reconnect the nodes. Follow the steps shown in tutoral_4. 

simulate the NAND layout

wave form

Using the LTpice and IRsim simulate the NAND gate. 

wave form

NOR gate design:

NAND gate can make the NOR gate much easier. Both gates use 4 MOSFETs and the change is the connection. 

And the size of PMOS is 20/2. Duplicate the NAND cell including the schematic, icon and layout cells. 

Then change the wire connection in the shematic. The right connection is shown in the following image.

The icon design of NOR

The NAND cell design, simulate the NOR gate. 

wave form

Layout of the NOR gate. 

LTspice for simulation.

wave form

XOR gate design:

Two extra inverters are needed in this design.  We can see 12 transistors will used in XOR gate. 

The size of PMOS is 20/10 and keep the size of NMOS unchanged. 

After designing NAND and NOR gates, the XOR is much easier. Duplicate the XOR gate again. 

And get 12 transistor in the new cell: XOR_wwl_f13. The correct circuit is shown in the following.

The icon view looks like NOR gate. 

Move to the simulation, let's design the layout. Because it has 12 transistors, we need more time. 

Put every transistors in the standard cell frames that snap together end-to-end. 

Press F5 to check DRC. 

By connecting one input to gnd and give a pulse to other input node. 

wave form

The LTspice simulation

wave form

Full adder design:

For the first full adder, use 2 XORs, 2 NANDs and 1 NOR with 3 inverters. 

Open a new cell: fulladder. And connect the wire Arcs as the figure shown in LAB6. 

Simulate by LTspice and IRSIM as seen below. 

wave form

For the second full adder with 3 NAND gates and 2 XOR gates. 

The layout design 

The LTspice and IRSIM is shown as below.

Backup all work and email it to yourself.

.jelib file

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