Lab

Lab 5 - EE 421L

Authored by: Medhanie Petros

E-mail: petrosm@unlv.nevada.edu

Date: 9/27/2013

Lab description

1. Back-up all of your work from the lab and the course.

2. Go through Tutorial 3

Postlab # 5

To begin save this library as tutorial_3.jelib in C:\Electric.
open the cell NMOS_IV.

Select the nMos Node and use Ctrl+C or Edit >>> to copy the Node to the clipboard.

Create a new schematic cell, Cell >>> Ctrl+N called inv_20_10, then paste the nMos Node copied above into this new cell and then fill the window

With the nMos Node selected go to Edit >>> press C and change the Node to transistor as seen below.

Make sure to hit Done.

Repeat the above set of steps for the pMos Node then you will get the following.

PMOS’s width to be 20 change, by editing the pMos Node’s properties, 10 to 20 as seen below.

Add the power symbol as seen below.

Turn the grid on then, with the power Node active just hit Ctrl+B to reduce the size of the power symbol.

Do for the gnd Node as you did for the power.

Add the wire Arcs to wire the inverter together.

The connection to the power Node is found in the center of the Node.

Add Off Page Nodes, then export the inverter’s input and output by using Ctrl+E to export the input.

Create an icon view for this schematic, by going to the menu item View >>> Make Icon View.

Change the icon by going to the menu Cell >>> Down Hierarchy >>> Down Hierarchy so that it looks like an inverter,

then select the icon view in the drawing area and press Ctrl+D to get the following.

then select and delete the box/text to get the following.

Select the bottom

Go to the Component menu and select the triangle and rotate position as seen below

Select the circle and place it in the icon view.

Edit the properties of the circle Ctrl+I to change x and y sizes to 1.

The icon view is now complete, the press Ctrl+U to go back up the schematic view of the inverter.

Simulate the operation of this inverter, and create a schematic call inverter_sim.

In the Explorer click, and hold, on the cell you want to instantiate and drag it into the drawing area.

Add wire arcs to the inverter’s input and output, and then place a SPICE code.

Using the menu item Tools >>> Simulation (Spice) >> Write Spice Deck

LTspice input and output.

this is also the other way showing it, after you close the LTspice.

To lay out the inverter you need to create a layout view for the inverter.

Add theNodes to the cell you created.

Select the pMos Node and set its SPICE model to PMOS and set the width to 20, select the nMos Node and set

its SPICE model to NMOS and set its width to 10, and keep both MOSFETs lengths at 2.

Set the x-size of both pAct Nodes to 20, both nAct Nodes to 10, and further set pWell and nWell x-sizes to 20.

Then add Arcs between transistors and active areas.

Move the active areas adjacent to the transistors

Rotate the transistors and active areas and move the devices into the positions, then hit F5 DRC

the layout to ensure no errors are present.

Connect the two poly gates together, the metal on the right of the devices together, and the metals on the left of the

transistors up or down to the well connections. Then hit F5 for DRC your design.

Add a poly1 to metal1 contact on the left and a metal1 Pin on the right.

Export in, out, gnd, and vdd, by hitting Ctrl+E

After all the it will look like this

Finally, to simulate this layout, you need to create a cell named inverter_sim with a layout view.

In the Explorer Drag inv_20_10{lay} over into the drawing area as seen below.

You can’t see what’s inside the cell but you can see the Exports.

With the cell selected use the eye and closed eye on the right side

of the menu to toggle between showing and not showing the contents of the cell.

With the cell selected edit the edit the cells properties (Ctrl+I).

Connect metal wires to the cell, then edit the properties of the wire Arcs so that they

correspond to the names in the inverter_sim{sch}.

Next copy the SPICE code from inverter_sim{sch} into this layout view of the cell.

Export the left Pins on the top and bottom metal1 Arcs with names vdd and gnd.

When you do all the DRC, NCC, and Well, you shouldn't get any errors.

Then the LTspice graph will look like the folloing.

Using the same application as you did the above schematic, and layout , the folloing fig. show that how to draft it.
It was used 20/10 (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 2), and
100/50 where the PMOS is 20/2 with M = 5 (5 MOSFETs in parallel to get 80 and 40, set multiplier as seen below).

To add the M=5, just go to the Tools >> Simulation (spice) >>> Add Multiplier, for both NMOS, and PMOS devices.

Same as the above method creat an Icon, then it would look the same as you did to above one.

Your layouts should have 4 exports: In, Out, vdd, and gnd. This is same as the above single layout, the only

difference is that this one is multiplied by five like the above layout you did.

The final wave form of the layout and schematic would look like the folloing fig.

Put diffrent capacitor load to your invertor;

With your 1pF capacitor

With your 10fF capacitor

With your 100fF capacitor

From the simulation result, you can see that when large size inverter could support larger load.

2. ALS simulation using three different load capacitors: 100fF, 1pF, 10pF.

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.jelib file

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