Lab 2 - EE 421L 

Authored by ; Medhanie Petros,

Date : Sep. 13, 2013

Email: petrosm@unlv.nevada.edu

Lab description

Lab 2 will help understand the design of a 10-bit Digital-to-Analog Converter (DAC). The Pre-Lab work will show the following:

  1) this first part shows the narrative of the steps

  2) second part, provieds  and discuss, simulation results different from the above to illustrate your understanding of the ADC and DAC

  3) explain how you determine the least significant bit (LSB, the minumum voltage change on the ADC's input to see a change in the digital code B[9:0]) of the converter. Use simulations to support your understanding.

Pre-lab Work

                                                            fig. 1

2) then select the sim_ADC_DCA{shc} file and then save the file. The following picture shows how it would look like.

                                                            fig. 2

3) When you run the sim it would plot the Vin and Vout traces , and it would look like the folloing picture

                                                            fig. 3

Simulation Results

From the Simulation above shows, Vin has a stright sin waveform form and Vout has a jagged waveform (Vin is leading Vout). 

The LSB represents the minumum voltage change on the ADC, and MSB represents to the leftmost bit of the digital

output. 1LSB=V_ref/2^N, where N is the number of bit. That gives 4.88mV LSB value, assuming the reference

voltage = 5V, and 10-b. The above fig.3 shows that the theory is true. 

Lab Report

R-2R Design

1) First design a 10-bit DAC using n-well resistor. To quick design a R-2R DAC circuit, go to CMOSedu.com and find out the Electric example of the CMOS Circuit 

Design, Layout and Simulation Book. Then Open the chapeter 30 and ee421_ecg621.jelib.  And then use the 

Cross-Library Copy command to get the Fig. 30_15 cell and subcells. 

2) change the resistor to n-well and to 10k value 

                                                            fig. 4

3) After you copy the ideal DAC from the sim_ADC_DAC, change all the design so that it would look like the following  fig. 5. 

                            fig. 5

check for errors by pushing f5, if error found check it again untill you get 0 error

4) In order to determine the output resistance of DRC,  assuming B0-B9 are connected to gnd, then combine all the parallel and series resistance and get the answer is R. To do that open a new cell called sim_R2R_DAC. 

5) The following fig. 6 shows that the DAC is gournded all its inputs and give a pulse source Vin (0 to 5V) to B9 node. As we know,

the peak voltage of Vout is 2.5V. Use a 10pF capacitor as the load, we can calculate the delay of DAC is 0.7RC=0.07us=70ns. The

simulation result in following image proves the calculation.

                                    fig. 6 

the above circuit verifies the hand calculation 

6) Simulation to verify the design first Copy the cell sim_ADC_DAC{sch} to a cell sim2_ADC_DAC{sch}. Use the R-2R DAC to

replace the ideal DAC.

                                                                                    fig. 7

                                    fig. 8

                                        fig. 9

                                                    fig. 10

                                            fig. 11

7) If you look at the fig. 12 switches are in series with the 2R horizontal resistors. That would increase the total output resistance, that means you will see the graph of Vout drops. In a real circuit if the switches use transistors, due to the transistor has its own resistance,  then each 2R resistors would increase the transistos resistance. Then then output voltage will go down. 

                                                                              fig. 12

.jelib file

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