Lab Project - ECE 421L
Authored
by Carlo Lopez-Tello.
Email: lopeztel@unlv.nevada.edu.
November 08, 2013.
Design of an 8 bit ALU that has the follwoing operations: a OR b, a AND b, a + b, a-b.
This ALU needs two 8 bit inputs a and b, one 8 bit output z, and two 1-bit inputs f0 and f1.
The signals f0 anf f1 are used to select the mode of operation of the ALU.
There are 5 components needed to make an ALU: OR gates, AND gates, inverters, 2to1 MUXes, and a full adder.
This is what a 1 bit ALU looks like.
![1bit%20ALUschem.JPG](1bit%20ALUschem.JPG)
A 4 to 1 MUX is used to select the output. To do subtraction a 2 to 1 Mux is used to select b', and
Cin is set to one when both f0 and f1 are high.
1bitALU_cell_icon.JPG
Icon for 1-bit ALU
![1bit%20ALUicon.JPG](1bit%20ALUicon.JPG)
Simulation of 1-bit ALU
![sim1bit%20ALUschem.JPG](sim1bit%20ALUschem.JPG)
![sim1bit%20ALUspice.JPG](sim1bit%20ALUspice.JPG)
To make the 4 to 1 MUX we use two 2 to 1 MUXes.
![4to2MUXshem.JPG](4to2MUXshem.JPG)
Icon for 4 to 1 MUX
![4to2MUXicon.JPG](4to2MUXicon.JPG)
Simulation of 4 to 1 MUX
![sim4to2MUXschem.JPG](sim4to2MUXschem.JPG)
![sim4to2MUXspice.JPG](sim4to2MUXspice.JPG)
The bottom two signals are the select, and the one above them is the output. Notice that it matches the selected input.
Since only the first Cin of the ALU has to be one when subtracting we can modify the 1-bit ALU so that we can use it
as a cell.
![1bitALU_cell_schem.JPG](1bitALU_cell_schem.JPG)
Icon for cell.
![1bitALU_cell_icon.JPG](1bitALU_cell_icon.JPG)
Now to make the 8-bit ALU.
![8bit_ALUschem.JPG](8bit_ALUschem.JPG)
Notice that the first Cin is 1 when subtracting.
Icon
![8bit_ALUicon.JPG](8bit_ALUicon.JPG)
Simulations of ALU
![sim_8bit_ALUschem.JPG](sim_8bit_ALUschem.JPG)
![sim_8bit_ALUspice.JPG](sim_8bit_ALUspice.JPG)
![sim_8bit_ALUschem2.JPG](sim_8bit_ALUschem2.JPG)
a = 01010001 b=10101100 a AND b = 00000000 a OR b = 11111101 a + b = 11111101 a-b = 10100101
![sim_8bit_ALUspice2.JPG](sim_8bit_ALUspice2.JPG)
Simulation using IRSIM
![sim_8bitalu_IRSIM.JPG](sim_8bitalu_IRSIM.JPG)
We need to layout the components of the ALU.
Layout of the inverter.
![inv_lay.JPG](inv_lay.JPG)
![inv_err.JPG](inv_err.JPG)
Layout of the NAND gate
![NAND_lay.JPG](NAND_lay.JPG)
![NAND_err.JPG](NAND_err.JPG)
Layout of the NOR gate
![NOR_lay.JPG](NOR_lay.JPG)
![NOR_err.JPG](NOR_err.JPG)
Layout of a 2 to 1 MUX
![2to1MUX_lay.JPG](2to1MUX_lay.JPG)
![2to1MUX_err.JPG](2to1MUX_err.JPG)
Layout of a 4 to 1 MUX
![4to1MUX_lay.JPG](4to1MUX_lay.JPG)
![4to1MUX_err.JPG](4to1MUX_err.JPG)
Layout of the full adder
![fulladder_lay.JPG](fulladder_lay.JPG)
![fulladder_err.JPG](fulladder_err.JPG)
Layout of the alu cell
![alucell_lay.JPG](alucell_lay.JPG)
![alucell_err.JPG](alucell_err.JPG)
Layout of the 8 bit alu
![8bit_alu_lay.JPG](8bit_alu_lay.JPG)
![8bit_alu_lay2.JPG](8bit_alu_lay2.JPG)
![8bit_alu_err.JPG](8bit_alu_err.JPG)
Link to jelib.
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