Lab 5 - ECE 421L 

Authored by Carlo Lopez-Tello.

Email: lopeztel@unlv.nevada.edu.

October 4, 2013.

  

Lab Description:

In this lab we will layout a CMOS inverter.


First, we need to make the schematic, so create a new cell.

Select the a NMOS device and PMOS device and connect them in the following way. Remember to export the off-page nodes.

 

genericcmos.JPG

 

Change the width of the PMOS to 20 and NMOs to 10, and set their corresponding spice models.

cmos_20-10.JPG

 

Create the following schematic for the inverter.

To make the symbol simply create a symbol cell with the same name as the schematic, or go to View>Make Icon View.

 

inv20-10sym.JPG

 

Make a new layout cell with the same name as the schematic cell.

The CMOS inverter is made of  NMOS and PMOS transistors, so we need a NMOS node, a PMOS node, two N-active nodes,

two P-active nodes, a P-well node, and a N-well node.

 

inv20-10partslay.JPG

 

Change the width of the nodes match the schematic, and set the corresponding spice models.

 

inv20-10partssizeslay.JPG

 

Make the NMOS and PMOS.

 

inv20-10partsNMOSPMOS.JPG

 

Now connect the parts to make the inverter. Make sure you export the same nodes in the schematic plus vdd and gnd.

 

inv20-10lay.JPG

 

Check your layout: DRC, NCC, and ERC.

 

inv20-10errorcheck.JPG

 

Now, we are going to simulate the operation of the inverter driving a 100f capacitor.

Create a new schematic, and add this file(C5_models.txt) to the same directory the jelib is in.

 

inv20-10sym100f.JPG

 

inv20-10sym100fgraph.JPG

 

Driving a 1p capacitor. 

 

inv20-10sym1p.JPG

 

inv20-10sym1pfgraph.JPG

 

Driving a 10p capacitor. 

 

inv20-10sym10p.JPG

 

inv20-10sym10pfgraph.JPG

 

We can also simulate the inverter using IRSIM. First add offpage nodes to the schematic, make sure vin is an input and vo is an output.

Run IRSIM by going to Tools>Simulation(Built-In)>IRSIM: simulate current cell.
 
Driving a 100f capacitor. 

 

inv20-10simIRSIM100fwav.JPG

 

Driving a 1p capacitor. 

  

inv20-10simIRSIM1pwav.JPG
 

Driving a 10p capacitor. 

 

inv20-10simIRSIM10pwav.JPG

 

Using ALS we can simualte logic, but not delays. To use ALS go to Tools>Simulation(Built-In)>ALS: simulate current cell.

ALS uses a 10 ns dealy for all logic.

 

inv20-10simALS100fwav.JPG

 

Now we are going to design a 100/50 inverter. First duplicate all the cells 20/10 inverter group.

The only modification needed in the schematic is a multiplier of five. To do this, select the PMOS and got to Tools>Simulation(Spice)>Add multiplier.

Add a multiplier of five to both NMOS and PMOS.

 

inv100-50schem.JPG

 

Make sure to change the text in yout symvol to 100/50.

 

inv100-50sym.JPG

 

To save area we can connect five 20/10 inverter in parallel instead of laying out a single 100/20 inverter.

 

inv100-50lay.JPG

 

Check your layout: DRC, NCC, and ERC.

 

inv100-50error.JPG

 

Just like before we are going to simulate the inverter driving 100f, 1pf, and 10pf loads.

 

inv100-50sim.JPG

 

Driving a 100f capacitor.

 

inv100-50_spice100f.JPG 

 

Driving a 1p capacitor.

 

inv100-50_spice1p.JPG

 

Driving a 10p capacitor.

 

inv100-50_spice10p.JPG

 

Using IRSIM.

Driving a 100f capacitor.

 

inv100-50_IRSIM100f.JPG

 

Driving a 1p capacitor.

 

inv100-50_IRSIM1p.JPG

 

Driving a 10p capacitor.

 

inv100-50_IRSIM10p.JPG

 

Using ALS.

 

inv100-50_ALS.JPG

Backup your work. 

Link to jelib.

 

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