Project - EE 421L

Authored by: Yun Lan

Email: lany3@unlv.nevada.edu

Date: 11/22/13

Lab description

In this project, we will design an 8-bit ALU with 4 functionalities: A AND B, AND OR B, A + (add) B, and A - (subtract) B. In part one, we will draw the schematic for ALU using the parts we designed before:AND, OR, Adder, Inverter, and some 2-to-1 Multiplexers.

• Multiplexer:
• 2-to-1_01 Multiplexer.

• I make a change to the multiplexer in lab 7 so that when S=0, A is selected and when S=1, B is selected.

• Simulate this new multiplexer to see that if it works properly.

• The result is same as expected result.

• 8-bit multiplexer schematic with the new 2-to-1 multiplexer.

• Verify the 8-bit multiplexer as well.

• The result is as expected: S=0, choose A; S=1, choose B.

• ALU schematics:

• I tried to make a new icon for a 4-to-1 multiplexer since the output Z is choose from the four inputs: AND, OR, Add, and Subtract. Later on I found out that there are only three inputs will connect to Z--since one adder can perform both add and subtract.

• Verify this 4-to-1 multiplexer.

• Simulation: when S1S0 = 00, out = A; 01, out = B; 10, out = C; 11, out = D.

• ALU schematic using the 4-to-1 multiplexer: there is one unnecessary 2-to-1 multiplexer inside the 4-to-1 multiplexer because the add and subtract share the same output as shown.

• Verify this ALU.

• The simulation result using SPICE is hard to understand for add and subtract parts.

• Therefore, we will use IRSIM to simulate the ALU. The following commands are the codes of the vector file for IRSIM. I use vectors and sets so that I can easily see whatI change.

• The result (read from bottom (Z[7]) to Z[0]) is same as the comments above. Different sets are separated by 5 ns so that there is enough time for the delay of each set.

• ALU schematic using three 2-to-1 multiplexers. The ALU has two 8-bit inputs: A and B, a 2-bit input F to control the multiplexers, and an 8-bit output Z. The subtractor can be implemented using the adder by inverting the B and add A, then plus 1. The multiplexer at the left corner decides the second input of the adder. If F[0] = 1, the adder will be used as the subtractor; else the adder will be used for addition. The signal F[0]=1 will also be used as the carry in of the adder for subtraction.

• Again, verify the new ALU. Use the same vector file to simulate.

• The result is same as the simulation of previous ALU.

• Now let's simulate the parts separately. First one is the AND gate.

• Simulation result is same as the expected result above.

• OR gate simulation.

• Simulation result is same as the expected result above.

• A + B simulation.

• Simulation result is same as the expected result above. The Cout (overflow) of the adder is not shown.

• A - B simulation.

• Simulation result is same as the expected result above. The Cout (overflow) of the adder is not shown.

• Backup...

• Layout of the ALU:
• I use metal-1 to make buses for A[0:7], B[0:7], F[0:1] and use metal-2 to connect to the components.

• A more readable layout view. This layout basically follows the same form as the schematic:

• The layout passes all DRC, NCC, and well check.

• Run a simulation for the layout and make the simulation result more readable:
• A AND B: 0xFF AND 0x56 = 0x56
• = 1111 1111 AND 0101 0110 = 0101 0110
• A OR B: 0x2A OR 0x55 = 0x7F
• = 0010 1010 OR 0101 0101 = 0111 1111
• A + B: 0x95 + 0xC1 = 0x56
• 1001 0101 + 1100 0001= (1)0101 0110
• A - B: 0xFF - 0x80 = 0x7F
• = 1111 1111 + (1000 0000)' + 1
• = 1111 1111 + 0111 1111 + 1
• = (1)0111 1110 + 1
• = (1)0111 1111

• Again, don't forget to back up your work.

The working library of the complete project can be found in this link: EE421L_Project_YL_F13.jelib.

Return to lany3/

Return to EE 421L Labs