Lab 8 - ECE 421L Digital Design Lab

Authored by 

Fred Hathaway, hathawa6@unlv.nevada.edu

Larin Lanoreaux, lamorea3@unlv.nevada.edu

Matt Mumm, mummm2@unlv.nevada.edu

Medhanie Petros, Petrosm@unlv.nevada.edu

MOSIS_chip1.jelib

5 Dec 2013 

  

Lab 8: Generate a test chip layout for submission to MOSIS for fabrication:

 

In this lab, we formed into a group of four students.  We will be taking our ALU designed from the lab projects, the 15volt bandgap comparator, and include nine different test strucures.

 

Below is the list of test structures that we must include on the chip.

 

 

We will be using a 1.5mm x 1.5mm chip with 40 bond pads.

 dip40.jpg

GROUND WILL ALWAYS BE Pin20

 

NMOS 100/2

Test Structure

-Connect ground and Sn to  pin 20

-Apply small gate voltage to pin23

-Measure Drain current on pin22

DN-Pin22
SN-Pin21
GN-Pin23
Body-Pin20

NMOS_schem.JPG
NMOS_layout.JPG

 

PMOS 100/2

Test Structure

-Connect vdd of 5v to Sp and to  pin 25

-Apply small gate voltage to pin26

-Measure Drain current on pin27

SP-Pin24
DP-Pin27
GP-Pin26
BP-Pin25


PMOS_schem.JPG

PMOS_layout.JPG

 

1k n+ resistor

Test Structure

-Ohm meter from pin 2 to pin 20 should= 1k


Vin-Pin2

Ground-Pin20

1k_np_resistor_schem.JPG
1k_np_resistor_layout.JPG

 

1k p+ resistor

To test structure

-connect vdd of 5v to pin40

-connect any voltage < 4v to pin 1

-Rout is internally connected to Pin 20

Rin-Pin1

Nwell-Pin40

Ground-Pin20

20k n-well resistor
20k_res_nwell.JPG

20k_res_nwell_layout.JPG

 

20k hi-res poly2 resistor

Test Structure

-Ohm meter from pin 32 to pin 20 should= 20k


Vin-Pin32

20k_hires_poly_schem.JPG

20k_hires_poly_layout.JPG

 

Bandgap reference

To test structure

-connect vdd of 5v to pin33

-connect ground to pin20
-Read voltage from ground to Vref. Vref should equal 1.25v

VDD_BG-Pin33
VREF-Pin34


Inverter

Test Structure

-Connect gnd to pin20

-Pulse low frequency to pin 30

-Measure pin 28


Power-Pin 29
In-Pin30
Out-Pin28

inverter_schem.JPG
inverter_layout.JPG

61 stage ring oscillator

To test structure

-connect vdd of 5v to pin39

-connect ground to pin20
-connect oscillscope to gnd and pin 38 to view oscillation.

OSC_out-Pin38

OSC VDD-Pin39

 

ALU_4Bit

Test Structure

-Connect gnd to pin20

F1F2Result
00AND
01OR
10ADD
11SUB

A[7:0]=1100 (12)

B[7:0]=1010 (10)

Bi[7:0]=0110  (+246,-10)


A and BA or BA + BA - B 
1000 11100110 (22)0010 (2)

Vdd-Pin10
F1-Pin19
F2-Pin18
A0-Pin8
B0-Pin9
A1-Pin11
B1-Pin12
A2-Pin13
B2-Pin14
A3-Pin15
B3-Pin16
Result0-Pin7
Result1-Pin6
Result2-Pin5
Result3-Pin4

Cout3-Pin17

ALU_schem.JPG

ALU_layout.JPG


 

15V bandgap comparator

Input a voltage of 15v to pin37

To test structure

-connect vdd of 5v to pin35

-connect ground to pin20
-If pin 37 is higher than 15.2v than pin 36 goes low
-If pin 37 is lower than 14.9v than pin 36 goes high

 

VDD BG Comp-Pin35

Enable Out-Pin36

15Vin-Pin37


AND Gate
VDD- Pin 3

A- Pin 5
B- Pin 6
AandB- Pin 4
 



Final Product 40 pin Chip
VDD- Pin 3

A- Pin 5
B- Pin 6
AandB- Pin 4





Jelib file can be found HERE


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