Lab

Lab 2 - ECE 421L

Authored by Aran Johnson

Email: john1701@unlv.nevada.edu

September 6th, 2013

Lab description:

This lab experiment will:

-provide a narrative of the steps done in the prelab

-provide, and discuss, simulation results different from the results done in the prelab

to illustrate your understanding of the ADC and DAC

-explain how you determine the least significant bit (LSB, the minimum voltage change

on the ADC's input to see a change in the digital code B[9:0]) of the converter.

Use simulations to support your understanding.

Narrative of Prelab Steps:

The first step of the prelab was to download the library lab2.jelib, and open,
in Electric, our lab/course jelib, our jelib is ee421_ecg621.jelib.
We then needed to navigate to menu command Cell -> Cross-Library Copy.
From there we copied sim_ADC_DAC{sch}, all of its subcells, and related
views into our lab/course jelib.

After this task was completed we navigated to "Done," and needed to save our current course/lab jelib.

Then, after backing up the work we have completed thus far, we ran the simulation using 'S' as a keybinding, or by selecting

"Write Spice Deck..."

Results differing from prelab:

In my own simulation that I performed, I demonstrated how an ADC works, it quantizes the values of the analog signal and

assigns a value to them, so that at its highest point the signal will read all 1 logics, and at its lowest point it will read all 0 logics.

This is illustrated in the picture below showing this exact result.

In order to find the LSB we must divide the Vdd by the number of possible binary numbers.

Lab:

We can now construct our own digital to analog converter based on the principles like the LSB
and basic circuit analysis. Below is a schematic for a digital to analog converter using 10K resistors.

We can now use LTspice's simulation to determine the delay of the output of this DAC using a pulse on the 9th bit.

The delay using a load resistor of 10K results in an expected delay to a half value of 0.7RC or roughly 35 nanoseconds.

Simulating gives us the results below.

When we zoom in it is easily seen that the approximate time to reach the half value of the final output is 0.7RC, which in this circuit

is about 35 nanoseconds.

We are now able to create an icon to stand for the whole circuit, to connect the outputs of the ADC to the inputs of our DAC we navigate to Export ->Create Export.
We can label each pin with an export that matches the output of the original ADC so that Electric now recognizes them as matching pins. Below is what the idon now looks like.

We can now run a simulation to see how our DAC matches against the input to the ADC.
First we will use only a 10K resistor at the output of our DAC. This results in a very choppy
signal because there is not charge storage to "smooth" out the signal.

Now, instead of just a resistor, only a capactior will be placed at the output.

The result is a smoother signal, but there is a noticeable delay, this delay is caused from the buildup of charge required by

a capacitor, and the slow dissipation of that charge.

Finally we will show the output when both a 10K resisitor and 10pF capacitor are placed at the output.

There is not much difference here, maybe a slight change in the delay, because the 10K resistor will not allow the capacitor to

discharge very quickly.

Lastly, it is important to realized that our DAC functions with the idea that the switches that provide the logic values from the ADC

has a resistance that is small compared to 10K, if this is proven to be untrue then our values of output resistance will beome unbalanced

and the output values will no longer be as reliable, resulting in some error in our output.

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