Lab 8 - ECE 421L Digital Design Lab

Authored by 

Fred Hathaway, hathawa6@unlv.nevada.edu

Larin Lanoreaux, lamorea3@unlv.nevada.edu

Matt Mumm, mummm2@unlv.nevada.edu

Medhanie Petros, Petrosm@unlv.nevada.edu

5 Dec 2013 

Lab 8: Generate a test chip layout for submission to MOSIS for fabrication:

In this lab, we formed into a group of four students.  We will be taking our ALU designed from the lab projects, the 15volt bandgap comparator, and include nine different test strucures.

Below is the list of test structures that we must include on the chip.

• 100/2 NMOS (3 pins, DN, GN, SN, connect the p+ body, B, of the NMOS to the chip's ground pin)
• 100/2 PMOS (4 pins, DP, GP, SP, and BP)
• Inverter made using 100/2 NMOS and 200/2 PMOS (3 pins, in, out, VDD_inv)
• 61 stage ring oscillator using 10/2 MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
• 20k n-well resistor (2 pins)
• 20k hi-res poly resistor (2 pins) 
• 1k n+ resistor (2 pins)
• 1k p+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)
• Bandgap reference (2 pins, VDD_bg and Vref)

We will be using a 1.5mm x 1.5mm chip with 40 bond pads.

GROUND WILL ALWAYS BE Pin20

NMOS 100/2

Test Structure

-Connect ground and Sn to  pin 20

-Apply small gate voltage to pin23

-Measure Drain current on pin22

DN-Pin22
SN-Pin21
GN-Pin23
Body-Pin20

PMOS 100/2

Test Structure

-Connect vdd of 5v to Sp and to  pin 25

-Apply small gate voltage to pin26

-Measure Drain current on pin27

SP-Pin24
DP-Pin27
GP-Pin26
BP-Pin25

1k n+ resistor

Test Structure

-Ohm meter from pin 2 to pin 20 = 1k

Vin-Pin2

Ground-Pin20

1k p+ resistor

To test structure

-connect vdd of 5v to pin40

-connect any voltage < 4v to pin 1

-Rout is internally connected to Pin 20

Pin-Pin1

Nwell-Pin40

Ground-Pin20

20k n-well resistor

20k hi-res poly2 resistor

Test Structure

-Ohm meter from pin 32 to pin 20 should= 20k

Vin-Pin32

Bandgap reference

To test structure

-connect vdd of 5v to pin33

VREF-Pin34

Inverter

Test Structure

-Connect gnd to pin20

-Pulse low frequency to pin 30

-Measure pin 28

Power-Pin 29
In-Pin30
Out-Pin28

61 stage ring oscillator

To test structure

-connect vdd of 5v to pin39

OSC_out-Pin38

OSC VDD-Pin39

ALU_4Bit

Test Structure

-Connect gnd to pin20

A[7:0]=1100 (12)

B[7:0]=1010 (10)

Bi[7:0]=0110  (+246,-10)

Vdd-Pin10
F1-Pin19
F2-Pin18
A0-Pin8
B0-Pin9
A1-Pin11
B1-Pin12
A2-Pin13
B2-Pin14
A3-Pin15
B3-Pin16
Result0-Pin7
Result1-Pin6
Result2-Pin5
Result3-Pin4

Cout3-Pin17

15V bandgap comparator

Input a voltage of 15v to pin37

To test structure

-connect vdd of 5v to pin35

VDD BG Comp-Pin35

Enable Out-Pin36

15Vin-Pin37

AND Gate
VDD- Pin 3

Final Product 40 pin Chip
VDD- Pin 3